James E. Rezek — 12 Patents at Unisys

James E. Rezek has been granted 12 US patents while listed as an inventor at Unisys. The first was granted in 1997 and the most recent in July 2006. James E. Rezek ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list James E. Rezek in Mounds View, MN, US.

Patents per Year

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Showing 1–12 of 12 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
7076410	Method and apparatus for efficiently viewing a number of selected components using a database editor tool	Joseph P. Kerzman	2006-07-11	$9,395,000
6910200	Method and apparatus for associating selected circuit instances and for performing a group operation thereon	Mark D. Aubel, Joseph P. Kerzman, James M. Nead	2005-06-21	$5,433,000
6889370	Method and apparatus for selecting and aligning cells using a placement tool	Joseph P. Kerzman	2005-05-03	$8,392,000
6701289	Method and apparatus for using a placement tool to manipulate cell substitution lists	Robert E. Garnett, Joseph P. Kerzman, Mark D. Aubel	2004-03-02	$11,479,000
6684376	Method and apparatus for selecting components within a circuit design database	Joseph P. Kerzman, Mark D. Aubel, Merwin H. Alferness	2004-01-27	$16,633,000
6546532	Method and apparatus for traversing and placing cells using a placement tool	Joseph P. Kerzman	2003-04-08	$9,584,000
6516456	Method and apparatus for selectively viewing nets within a database editor tool	Robert E. Garnett, Joseph P. Kerzman, Mark D. Aubel	2003-02-04	$17,617,000
5956256	Method and apparatus for optimizing a circuit design having multi-paths therein	Kevin C. Cleereman, Kenneth E. Merryman, Kenneth L. Engelbrecht	1999-09-21	$53,035,000
5912820	Method and apparatus for distributing a clock tree within a hierarchical circuit design	Joseph P. Kerzman, John T. Rusterholz	1999-06-15	$51,214,000
5819072	Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints	Louis Bernard Bushard, Peter B. Criswell, Douglas A. Fuller, Richard F. Paul	1998-10-06	$19,456,000
5805861	Method of stabilizing component and net names of integrated circuits in electronic design automation systems	Douglas J. Gilbert, Harold E. Reindel, Allen B. Tabbert	1998-09-08	$65,779,000
5696693	Method for placing logic functions and cells in a logic design using floor planning by analogy	Mark D. Aubel, Arthur F. Boehm, Joseph P. Kerzman, John T. Rusterholz, Richard F. Paul	1997-12-09	$5,682,000

James E. Rezek — 12 Patents

Patents per Year

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