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Method and apparatus for selectively providing hierarchy to a circuit design |
Ted G. Lautzenheiser, Michael K. Engh |
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Spreadsheet driven I/O buffer synthesis process |
Ronald G. Arnold |
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Method and apparatus for incremntally optimizing a circuit design |
Kevin C. Cleereman, Steve D. Thatcher |
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Method and apparatus for optimizing a gated clock structure using a standard optimization tool |
Kevin C. Cleereman, Kenneth L. Engelbrecht |
1999-11-09 |
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Method and apparatus for providing optimization parameters to a logic optimizer tool |
Kevin C. Cleereman |
1999-09-28 |
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Method and apparatus for monitoring the performance of a circuit optimization tool |
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Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool |
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