Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9424389 | Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeper | Anthony Gus Aipperspach, Derick G. Behrends, Todd A. Christensen | 2016-08-23 |
| 9396303 | Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeper | Anthony Gus Aipperspach, Derick G. Behrends, Todd A. Christensen | 2016-07-19 |
| 9251869 | Deep sleep wakeup of multi-bank memory | Chad A. Adams, Thinh V. Luong | 2016-02-02 |
| 9183896 | Deep sleep wakeup of multi-bank memory | Chad A. Adams, Thinh V. Luong | 2015-11-10 |
| 8488368 | Method for selectable guaranteed write-through with early read suppression | Todd A. Christensen, Peter Thomas Freiburger | 2013-07-16 |
| 7971164 | Assessing resources required to complete a VLSI design | Derick G. Behrends, Travis R. Hebig, Daniel Mark Nelson | 2011-06-28 |
| 7925950 | Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic | Todd A. Christensen, Peter Thomas Freiburger | 2011-04-12 |
| 7911827 | Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels | Derick G. Behrends, Travis R. Hebig, Daniel Mark Nelson | 2011-03-22 |
| 7844869 | Implementing enhanced LBIST testing of paths including arrays | Louis Bernard Bushard, Todd A. Christensen | 2010-11-30 |
| 7737757 | Low power level shifting latch circuits with gated feedback for high speed integrated circuits | Derick G. Behrends, Travis R. Hebig, Daniel Mark Nelson | 2010-06-15 |
| 7724585 | Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability | Derick G. Behrends, Travis R. Hebig, Daniel Mark Nelson | 2010-05-25 |
| 7535776 | Circuit for improved SRAM write around with reduced read access penalty | Derick G. Behrends, Travis R. Hebig, Daniel Mark Nelson | 2009-05-19 |