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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Jesse D. Smith — 12 Patents

IBM: 12 patents #9,258 of 70,183Top 15%
Rochester, MN: #489 of 3,042 inventorsTop 20%
Minnesota: #6,327 of 52,454 inventorsTop 15%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
Jesse D. Smith has been granted 12 US patents while listed as an inventor at IBM. The first was granted in 2009 and the most recent in August 2016. Jesse D. Smith ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Jesse D. Smith in Rochester, MN, US.

Patents per Year

Patents granted per year, 2009 to 2016Bar chart with a peak of 3 patents in 2010.peak 32009: 1 patents20092010: 3 patents20102011: 3 patents20112013: 1 patents20132015: 1 patents20152016: 3 patents2016

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9424389 Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeper Anthony Gus Aipperspach, Derick G. Behrends, Todd A. Christensen 2016-08-23 $3,302,000
9396303 Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeper Anthony Gus Aipperspach, Derick G. Behrends, Todd A. Christensen 2016-07-19 $4,161,000
9251869 Deep sleep wakeup of multi-bank memory Chad A. Adams, Thinh V. Luong 2016-02-02 $1,325,000
9183896 Deep sleep wakeup of multi-bank memory Chad A. Adams, Thinh V. Luong 2015-11-10 $5,091,000
8488368 Method for selectable guaranteed write-through with early read suppression Todd A. Christensen, Peter Thomas Freiburger 2013-07-16 $5,283,000
7971164 Assessing resources required to complete a VLSI design Derick G. Behrends, Travis R. Hebig, Daniel Mark Nelson 2011-06-28 $4,369,000
7925950 Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic Todd A. Christensen, Peter Thomas Freiburger 2011-04-12 $5,593,000
7911827 Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levels Derick G. Behrends, Travis R. Hebig, Daniel Mark Nelson 2011-03-22 $5,211,000
7844869 Implementing enhanced LBIST testing of paths including arrays Louis Bernard Bushard, Todd A. Christensen 2010-11-30 $3,507,000
7737757 Low power level shifting latch circuits with gated feedback for high speed integrated circuits Derick G. Behrends, Travis R. Hebig, Daniel Mark Nelson 2010-06-15 $4,416,000
7724585 Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability Derick G. Behrends, Travis R. Hebig, Daniel Mark Nelson 2010-05-25 $4,007,000
7535776 Circuit for improved SRAM write around with reduced read access penalty Derick G. Behrends, Travis R. Hebig, Daniel Mark Nelson 2009-05-19 $10,497,000