Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10916323 | Memory interface latch with integrated write-through and fence functions | Elizabeth L. Gerhard, Todd A. Christensen, Chad A. Adams | 2021-02-09 |
| 10381098 | Memory interface latch with integrated write-through and fence functions | Elizabeth L. Gerhard, Todd A. Christensen, Chad A. Adams | 2019-08-13 |
| 10229748 | Memory interface latch with integrated write-through function | Elizabeth L. Gerhard, Todd A. Christensen, Chad A. Adams | 2019-03-12 |
| 9087563 | SRAM local evaluation and write logic for column selection | Travis R. Hebig | 2015-07-21 |
| 9058866 | SRAM local evaluation logic for column selection | Travis R. Hebig | 2015-06-16 |
| 8488368 | Method for selectable guaranteed write-through with early read suppression | Todd A. Christensen, Jesse D. Smith | 2013-07-16 |
| 8427894 | Implementing single bit redundancy for dynamic SRAM circuit with any bit decode | Derick G. Behrends, Todd A. Christensen, Travis R. Hebig, Jayson K. Wittrup | 2013-04-23 |
| 8107309 | Bias temperature instability-influenced storage cell | Douglas M. Dewanz, David P. Paulsen, John E. Sheets, II | 2012-01-31 |
| 7925950 | Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic | Todd A. Christensen, Jesse D. Smith | 2011-04-12 |
| 7835176 | Implementing enhanced dual mode SRAM performance screen ring oscillator | Chad A. Adams, Todd A. Christensen, Travis R. Hebig | 2010-11-16 |
| 7724586 | Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usage | Chad A. Adams, Todd A. Christensen, Daniel Mark Nelson | 2010-05-25 |
| 7684263 | Method and circuit for implementing enhanced SRAM write and read performance ring oscillator | Chad A. Adams, Todd A. Christensen, Travis R. Hebig | 2010-03-23 |
| 7681095 | Methods and apparatus for testing integrated circuits | Derick G. Behrends, Ryan Charles Kivimagi | 2010-03-16 |
| 7443744 | Method for reducing wiring and required number of redundant elements | Derick G. Behrends, Ryan Charles Kivimagi, Daniel Mark Nelson | 2008-10-28 |
| 7418637 | Methods and apparatus for testing integrated circuits | Derick G. Behrends, Ryan Charles Kivimagi | 2008-08-26 |
| 7161390 | Dynamic latching logic structure with static interfaces for implementing improved data setup time | Anthony Gus Aipperspach | 2007-01-09 |
| 7035127 | Method and sum addressed cell encoder for enhanced compare and search timing for CAM compare | Chad A. Adams, Derick G. Behrends, Todd A. Christensen, Ryan Charles Kivimagi | 2006-04-25 |
| 7015600 | Pulse generator circuit and semiconductor device including same | Chad A. Adams, Todd A. Christensen | 2006-03-21 |
| 6901003 | Lower power and reduced device split local and continuous bitline for domino read SRAMs | Chad A. Adams, Anthony Gus Aipperspach, Todd A. Christensen | 2005-05-31 |
| 6741493 | Split local and continuous bitline requiring fewer wires | Todd A. Christensen | 2004-05-25 |
| 6657886 | Split local and continuous bitline for fast domino read SRAM | Chad A. Adams, Anthony Gus Aipperspach, Todd A. Christensen | 2003-12-02 |
| 6538522 | Method and ring oscillator for evaluating dynamic circuits | Anthony Gus Aipperspach, Todd A. Christensen, David M. Friend, Nghia V. Phan | 2003-03-25 |
| 6272654 | Fast scannable output latch with domino logic input | — | 2001-08-07 |
| 6247166 | Method and apparatus for assembling array and datapath macros | Anthony Gus Aipperspach | 2001-06-12 |
| 6172531 | Low power wordline decoder circuit with minimized hold time | Anthony Gus Aipperspach | 2001-01-09 |