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Signal transmission reducing coupling caused delay variation |
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Multiple-patterned semiconductor device channels |
David H. Allen, David P. Paulsen, John E. Sheets, II, Kelly L. Williams |
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Multiple-patterned semiconductor device channels |
David H. Allen, David P. Paulsen, John E. Sheets, II, Kelly L. Williams |
2015-08-18 |
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Semiconductor device channels |
David H. Allen, David P. Paulsen, John E. Sheets, II, Kelly L. Williams |
2015-08-11 |
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Semiconductor device with distinct multiple-patterned conductive tracks on a same level |
David H. Allen, David P. Paulsen, John E. Sheets, II |
2015-08-04 |
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Signal path and method of manufacturing a multiple-patterned semiconductor device |
David H. Allen, David P. Paulsen, John E. Sheets, II |
2015-08-04 |
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Semiconductor device channels |
David H. Allen, David P. Paulsen, John E. Sheets, II, Kelly L. Williams |
2015-08-04 |
| 9093451 |
Signal path and method of manufacturing a multiple-patterned semiconductor device |
David H. Allen, David P. Paulsen, John E. Sheets, II |
2015-07-28 |
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Method of making semiconductor device with distinct multiple-patterned conductive tracks on a same level |
David H. Allen, David P. Paulsen, John E. Sheets, II |
2015-07-21 |
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Signal path of a multiple-patterned semiconductor device |
David H. Allen, David P. Paulsen, John E. Sheets, II |
2015-07-14 |
| 9076848 |
Semiconductor device channels |
David H. Allen, David P. Paulsen, John E. Sheets, II, Kelly L. Williams |
2015-07-07 |
| 9070751 |
Semiconductor device channels |
David H. Allen, David P. Paulsen, John E. Sheets, II, Kelly L. Williams |
2015-06-30 |
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Signal path of a multiple-patterned semiconductor device |
David H. Allen, David P. Paulsen, John E. Sheets, II |
2015-04-28 |
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Signal path and method of manufacturing a multiple-patterned semiconductor device |
David H. Allen, David P. Paulsen, John E. Sheets, II |
2014-10-21 |
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Method for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications |
David H. Allen, David P. Paulsen, John E. Sheets, II |
2014-08-19 |
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Bias temperature instability-influenced storage cell |
Peter Thomas Freiburger, David P. Paulsen, John E. Sheets, II |
2012-01-31 |
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Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under test |
Anthony Gus Aipperspach, Todd A. Christensen |
2003-11-04 |
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High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatus |
Anthony Gus Aipperspach, Fariborz Assaderaghi, Todd A. Christensen, Jente B. Kuang |
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Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under test |
Anthony Gus Aipperspach, Todd A. Christensen |
2001-08-14 |
| 4849904 |
Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices |
Anthony Gus Aipperspach, Joseph M. Fitzgerald |
1989-07-18 |