Issued Patents All Time
Showing 25 most recent of 151 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11551101 | Real time cognitive reasoning using a circuit with varying confidence level alerts | Karl R. Erickson, Phil C. Paone, George Paulik, David P. Paulsen, Gregory J. Uhlmann | 2023-01-10 |
| 11526768 | Real time cognitive reasoning using a circuit with varying confidence level alerts | Karl R. Erickson, Phil C. Paone, George Paulik, David P. Paulsen, Gregory J. Uhlmann | 2022-12-13 |
| 11061645 | Optimizing data approximation analysis using low power circuitry | Karl R. Erickson, Phil C. Paone, David P. Paulsen, Gregory J. Uhlmann | 2021-07-13 |
| 10802062 | Cognitive analysis using applied analog circuits | Karl R. Erickson, Phil C. Paone, George Paulik, David P. Paulsen, Raymond A. Richetta +1 more | 2020-10-13 |
| 10732931 | Negative operand compatible charge-scaling subtractor circuit | Phil C. Paone, David P. Paulsen, George Paulik, Karl R. Erickson, Gregory J. Uhlmann | 2020-08-04 |
| 10671348 | Charge-scaling multiplier circuit with dual scaled capacitor sets | David P. Paulsen, Phil C. Paone, George Paulik, Karl R. Erickson | 2020-06-02 |
| 10670642 | Real time cognitive monitoring of correlations between variables | Karl R. Erickson, Phil C. Paone, George Paulik, David P. Paulsen, Raymond A. Richetta +1 more | 2020-06-02 |
| 10663502 | Real time cognitive monitoring of correlations between variables | Karl R. Erickson, Phil C. Paone, David P. Paulsen, George Paulik, Raymond A. Richetta +1 more | 2020-05-26 |
| 10658993 | Charge-scaling multiplier circuit with digital-to-analog converter | David P. Paulsen, Phil C. Paone, George Paulik, Karl R. Erickson | 2020-05-19 |
| 10598710 | Cognitive analysis using applied analog circuits | Karl R. Erickson, Phil C. Paone, George Paulik, David P. Paulsen, Raymond A. Richetta +1 more | 2020-03-24 |
| 10592209 | Charge-scaling multiplier circuit | David P. Paulsen, Phil C. Paone, George Paulik, Karl R. Erickson | 2020-03-17 |
| 10587282 | Charge-scaling adder circuit | David P. Paulsen, Phil C. Paone, George Paulik, Karl R. Erickson, Gregory J. Uhlmann | 2020-03-10 |
| 10566987 | Charge-scaling subtractor circuit | David P. Paulsen, Phil C. Paone, George Paulik, Karl R. Erickson, Gregory J. Uhlmann | 2020-02-18 |
| 10418094 | Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells | Karl R. Erickson, Phil C. Paone, David P. Paulsen, Gregory J. Uhlmann | 2019-09-17 |
| 10367520 | Charge-scaling subtractor circuit | David P. Paulsen, Phil C. Paone, George Paulik, Karl R. Erickson, Gregory J. Uhlmann | 2019-07-30 |
| 10348320 | Charge-scaling adder circuit | David P. Paulsen, Phil C. Paone, George Paulik, Karl R. Erickson, Gregory J. Uhlmann | 2019-07-09 |
| 10304522 | Method for low power operation and test using DRAM device | Karl R. Erickson, Phil C. Paone, David P. Paulsen, Gregory J. Uhlmann | 2019-05-28 |
| 10236887 | Generating a unique die identifier for an electronic chip | Karl R. Erickson, Phil C. Paone, David P. Paulsen, Gregory J. Uhlmann | 2019-03-19 |
| 10236050 | Optimizing data approximation analysis using low power circuitry | Karl R. Erickson, Phil C. Paone, George Paulik, David P. Paulsen, Gregory J. Uhlmann | 2019-03-19 |
| 10224089 | Optimizing data approximation analysis using low bower circuitry | Karl R. Erickson, Phil C. Paone, George Paulik, David P. Paulsen, Gregory J. Uhlmann | 2019-03-05 |
| 10224410 | Through-substrate via power gating and delivery bipolar transistor | Gerald K. Bartley, David P. Paulsen | 2019-03-05 |
| 10170578 | Through-substrate via power gating and delivery bipolar transistor | Gerald K. Bartley, David P. Paulsen | 2019-01-01 |
| 10121530 | Implementing eFuse visual security of stored data using EDRAM | Todd A. Christensen, Karl R. Erickson, Phil C. Paone, David P. Paulsen, Gregory J. Uhlmann | 2018-11-06 |
| 10090063 | System for testing charge trap memory cells | Karl R. Erickson, Phil C. Paone, David P. Paulsen, Gregory J. Uhlmann | 2018-10-02 |
| 10061368 | Enhancing performance of one or more slower partitions of an integrated circuit to improve performance of the integrated circuit | Todd A. Christensen | 2018-08-28 |