Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11112854 | Operating pulsed latches on a variable power supply | Steven M. Douskey, Mary P. Kusko, Hari Krishnan Rajeev, James D. Warnock | 2021-09-07 |
| 10816599 | Dynamically power noise adaptive automatic test pattern generation | Steven M. Douskey, Sumit Panigrahi, Mary P. Kusko | 2020-10-27 |
| 10746794 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Mary P. Kusko, Cedric Lichtenau | 2020-08-18 |
| 10739401 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Mary P. Kusko, Cedric Lichtenau | 2020-08-11 |
| 10649028 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Mary P. Kusko, Cedric Lichtenau | 2020-05-12 |
| 10545190 | Circuit structures to resolve random testability | Mary P. Kusko, Spencer K. Millican | 2020-01-28 |
| 10527674 | Circuit structures to resolve random testability | Mary P. Kusko, Spencer K. Millican | 2020-01-07 |
| 10521381 | Self-moderating bus arbitration architecture | Venkatasreekanth Prudvi | 2019-12-31 |
| 10386912 | Operating pulsed latches on a variable power supply | Steven M. Douskey, Mary P. Kusko, Hari Krishnan Rajeev, James D. Warnock | 2019-08-20 |
| 10303631 | Self-moderating bus arbitration architecture | Venkatasreekanth Prudvi | 2019-05-28 |
| 10216885 | Adjusting scan connections based on scan control locations | Ankit N. Kagliwal, Sridhar H. Rangarajan, James D. Warnock | 2019-02-26 |
| 10088524 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Satya R. S. Bhamidipati, Mary P. Kusko, Cedric Lichtenau | 2018-10-02 |
| 10060971 | Adjusting latency in a scan cell | Steven M. Douskey, Mary P. Kusko | 2018-08-28 |
| 10001523 | Adjusting latency in a scan cell | Steven M. Douskey, Mary P. Kusko | 2018-06-19 |
| 9934348 | Adjusting scan connections based on scan control locations | Ankit N. Kagliwal, Sridhar H. Rangarajan, James D. Warnock | 2018-04-03 |
| 9322876 | Control test point for timing stability during scan capture | Purushotam Bheemanna, Pavan K. Guntipalli | 2016-04-26 |
| 9218447 | Automatic test pattern generation (ATPG) considering crosstalk effects | Kanad Basu, Hari Krishnan Rajeev | 2015-12-22 |
| 9194915 | Control test point for timing stability during scan capture | Purushotam Bheemanna, Pavan K. Guntipalli | 2015-11-24 |
| 9086458 | Q-gating cell architecture to satiate the launch-off-shift (LOS) testing and an algorithm to identify best Q-gating candidates | Kshitij Kulshreshtha, Balaji Upputuri | 2015-07-21 |
| 8898604 | Algorithm to identify best Q-gating candidates and a Q-gating cell architecture to satiate the launch-off-shift (LOS) testing | Kshitij Kulshreshtha, Balaji Upputuri | 2014-11-25 |
| 8776006 | Delay defect testing of power drop effects in integrated circuits | Thamaraiselvan Subramani, Balaji Upputuri | 2014-07-08 |