Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10746794 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Raghu G. GopalaKrishnaSetty, Mary P. Kusko, Cedric Lichtenau | 2020-08-18 |
| 10739401 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Raghu G. GopalaKrishnaSetty, Mary P. Kusko, Cedric Lichtenau | 2020-08-11 |
| 10649028 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Raghu G. GopalaKrishnaSetty, Mary P. Kusko, Cedric Lichtenau | 2020-05-12 |
| 10598727 | Identification of unknown sources for logic built-in self test in verification | Mary P. Kusko, Cedric Lichtenau, Srinivas V. N. Polisetty | 2020-03-24 |
| 10088524 | Logic built in self test circuitry for use in an integrated circuit with scan chains | Raghu G. GopalaKrishnaSetty, Mary P. Kusko, Cedric Lichtenau | 2018-10-02 |
| 10018672 | Reducing power requirements and switching during logic built-in-self-test and scan test | Mary P. Kusko, Cedric Lichtenau | 2018-07-10 |
| 10018671 | Reducing power requirements and switching during logic built-in-self-test and scan test | Mary P. Kusko, Cedric Lichtenau | 2018-07-10 |
| 9689920 | Identification of unknown sources for logic built-in self test in verification | Mary P. Kusko, Cedric Lichtenau, Srinivas V. N. Polisetty | 2017-06-27 |
| 9651616 | Reducing power requirements and switching during logic built-in-self-test and scan test | Mary P. Kusko, Cedric Lichtenau | 2017-05-16 |
| 9651623 | Reducing power requirements and switching during logic built-in-self-test and scan test | Mary P. Kusko, Cedric Lichtenau | 2017-05-16 |
| 9268892 | Identification of unknown sources for logic built-in self test in verification | Mary P. Kusko, Cedric Lichtenau, Srinivas V. N. Polisetty | 2016-02-23 |