Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12241931 | Method and apparatus for capture clock control to minimize toggling during testing | Scott Mack | 2025-03-04 |
| 12025661 | Power-sensitive scan-chain testing | Sreekanth G. Pai, Kushal Kamal | 2024-07-02 |
| 11768239 | Method and apparatus for timing-annotated scan-chain testing using parallel testbench | Sreekanth G. Pai, Mallikarjunarao Thummalapalli | 2023-09-26 |
| 11662382 | Method and apparatus for contemporary test time reduction for JTAG | Umesh Prabhakar Hade | 2023-05-30 |
| 9086458 | Q-gating cell architecture to satiate the launch-off-shift (LOS) testing and an algorithm to identify best Q-gating candidates | Raghu G. GopalaKrishnaSetty, Kshitij Kulshreshtha | 2015-07-21 |
| 8990648 | Optimized synchronous scan flip flop circuit | Ravi Lakshmipathy | 2015-03-24 |
| 8898604 | Algorithm to identify best Q-gating candidates and a Q-gating cell architecture to satiate the launch-off-shift (LOS) testing | Raghu G. GopalaKrishnaSetty, Kshitij Kulshreshtha | 2014-11-25 |
| 8776006 | Delay defect testing of power drop effects in integrated circuits | Raghu G. GopalaKrishnaSetty, Thamaraiselvan Subramani | 2014-07-08 |