Issued Patents All Time
Showing 26–50 of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10268482 | Multi-slice processor issue of a dependent instruction in an issue queue based on issue of a producer instruction | Brian D. Barrick, Michael J. Genden, Jerry Y. Lu, Dung Q. Nguyen, Nasrin Sultana +2 more | 2019-04-23 |
| 10268518 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone | 2019-04-23 |
| 10255107 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone | 2019-04-09 |
| 10248421 | Operation of a multi-slice processor with reduced flush and restore latency | Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Cliff Kucharski, Dung Q. Nguyen +2 more | 2019-04-02 |
| 10241790 | Operation of a multi-slice processor with reduced flush and restore latency | Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Cliff Kucharski, Dung Q. Nguyen +2 more | 2019-03-26 |
| 10223196 | ECC scrubbing method in a multi-slice microprocessor | Brian D. Barrick, James Wilson Bishop, Maarten J. Boersma, Marcy E. Byers, Jentje Leenstra +2 more | 2019-03-05 |
| 10223125 | Linkable issue queue parallel execution slice processing method | Jeffrey C. Brownscheidle, Maureen A. Delaney, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto | 2019-03-05 |
| 10209995 | Processor core including pre-issue load-hit-store (LHS) hazard prediction to reduce rejection of load instructions | Richard J. Eickemeyer, John B. Griswell, Jr., Dung Q. Nguyen | 2019-02-19 |
| 10175985 | Mechanism for using a reservation station as a scratch register | Michael J. Genden, Dung Q. Nguyen | 2019-01-08 |
| 10140127 | Operation of a multi-slice processor with selective producer instruction types | Brian D. Barrick, Maureen A. Delaney, Thao T. Doan, Michael J. Genden, Rokesh Jayasundar +2 more | 2018-11-27 |
| 10133581 | Linkable issue queue parallel execution slice for a processor | Jeffrey C. Brownscheidle, Maureen A. Delaney, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto | 2018-11-20 |
| 10133576 | Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries | Salma Ayub, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Dung Q. Nguyen +1 more | 2018-11-20 |
| 10127047 | Operation of a multi-slice processor with selective producer instruction types | Brian D. Barrick, Maureen A. Delaney, Thao T. Doan, Michael J. Genden, Rokesh Jayasundar +2 more | 2018-11-13 |
| 10120693 | Fast multi-width instruction issue in parallel slice processor | Salma Ayub, Jeffrey C. Brownscheidle, Dung Q. Nguyen, Tu-An T. Nguyen, Salim A. Shah +1 more | 2018-11-06 |
| 10078516 | Techniques to wake-up dependent instructions for back-to-back issue in a microprocessor | Jeffrey C. Brownscheidle, Maureen A. Delaney, Dung Q. Nguyen | 2018-09-18 |
| 10073697 | Handling unaligned load operations in a multi-slice computer processor | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2018-09-11 |
| 10067763 | Handling unaligned load operations in a multi-slice computer processor | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more | 2018-09-04 |
| 10042770 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone | 2018-08-07 |
| 10037229 | Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions | Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone | 2018-07-31 |
| 10031757 | Operation of a multi-slice processor implementing a mechanism to overcome a system hang | Jeffrey C. Brownscheidle, Maureen A. Delaney, Dhivya Jeganathan, Dung Q. Nguyen, Salim A. Shah | 2018-07-24 |
| 9996359 | Fast multi-width instruction issue in parallel slice processor | Salma Ayub, Jeffrey C. Brownscheidle, Dung Q. Nguyen, Tu-An T. Nguyen, Salim A. Shah +1 more | 2018-06-12 |
| 9983875 | Operation of a multi-slice processor preventing early dependent instruction wakeup | David A. Hrusecky, Elizabeth A. McGlone, Jennifer L. Molnar | 2018-05-29 |
| 9983879 | Operation of a multi-slice processor implementing dynamic switching of instruction issuance order | Jeffrey C. Brownscheidle, Maureen A. Delaney, Dhivya Jeganathan, Dung Q. Nguyen, Salim A. Shah | 2018-05-29 |
| 9971600 | Techniques to wake-up dependent instructions for back-to-back issue in a microprocessor | Jeffrey C. Brownscheidle, Maureen A. Delaney, Dung Q. Nguyen | 2018-05-15 |
| 9971604 | History buffer for multiple-field registers | Michael J. Genden, Dung Q. Nguyen, David R. Terry, Kenneth L. Ward | 2018-05-15 |