Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11269715 | Systems and methods for adaptive proactive failure analysis for memories | Vijay Nijhawan, Wade Andrew Butcher | 2022-03-08 |
| 11210153 | Method and apparatus for predictive failure handling of interleaved dual in-line memory modules | Vijay Nijhawan, Chandrashekar Nelogal, Syama Poluri | 2021-12-28 |
| 11144410 | System and method to dynamically increase memory channel robustness at high transfer rates | Bhyrav M. Mutnury, Stuart Allen Berke | 2021-10-12 |
| 11093419 | System and method for cost and power optimized heterogeneous dual-channel DDR DIMMs | Mukund P. Khatri | 2021-08-17 |
| 10854242 | Intelligent dual inline memory module thermal controls for maximum uptime | Hasnain Shabbir, Amit Sumanlal Shah, Mark Dykstra | 2020-12-01 |
| 10783025 | Method and apparatus for predictive failure handling of interleaved dual in-line memory modules | Vijay Nijhawan, Chandrashekar Nelogal, Syama Poluri | 2020-09-22 |
| 10761919 | System and method to control memory failure handling on double-data rate dual in-line memory modules | Rene Franco, Amit Sumanlal Shah, Tuyet-Huong Thi Nguyen, Vijay Nijhawan, Mark L. Farley +1 more | 2020-09-01 |
| 10732859 | Systems and methods for granular non-volatile memory health visibility to a host | Krishna P. Kakarla, Balaji Bapu Gururaja Rao, Elie Antoun Jreij | 2020-08-04 |
| 10725671 | Dual inline memory provisioning and reliability, availability, and serviceability enablement based on post package repair history | Amit Sumanlal Shah, Ananya Mukherjee, Mark L. Farley | 2020-07-28 |
| 10705901 | System and method to control memory failure handling on double-data rate dual in-line memory modules via suspension of the collection of correctable read errors | Amit Sumanlal Shah, Tuyet-Huong Thi Nguyen, James R. Pledge | 2020-07-07 |
| 10685736 | Maintaining highest performance of DDR5 channel with marginal signal integrity | Stuart Allen Berke, Bhyrav M. Mutnury | 2020-06-16 |
| 10678467 | Systems and methods for selective save operations in a persistent memory | Krishna P. Kakarla, Balaji Bapu Gururaja Rao, Elie Antoun Jreij | 2020-06-09 |
| 10657009 | System and method to dynamically increase memory channel robustness at high transfer rates | Bhyrav M. Mutnury, Stuart Allen Berke | 2020-05-19 |
| 10621118 | System and method of utilizing different memory media with a device | Shyamkumar T. Iyer, Yogesh Varma | 2020-04-14 |
| 10579392 | System and method for mapping physical memory with mixed storage class memories | Stuart Allen Berke, Jeffrey Guo | 2020-03-03 |
| 10558521 | System and method for providing predictive failure detection on DDR5 DIMMs using on-die ECC | Stuart Allen Berke, Andrew Butcher | 2020-02-11 |
| 10545882 | Systems and methods for load-balancing cache flushes to non-volatile memory | Wade Andrew Butcher, Stuart Allen Berke | 2020-01-28 |
| 10528283 | System and method to provide persistent storage class memory using NVDIMM-N with an NVDIMM-P footprint | Andrew Butcher, Syama Poluri, Krishna P. Kakarla | 2020-01-07 |
| 10496477 | System and method of utilizing memory modules | Stuart Allen Berke, Bhyrav M. Mutnury | 2019-12-03 |
| 10474384 | System and method for providing a back door communication path between channels on dual-channel DIMMs | Stuart Allen Berke, Bhyrav M. Mutnury | 2019-11-12 |
| 10474583 | System and method for controlling cache flush size | John E. Jenne, Stuart Allen Berke | 2019-11-12 |
| 10452294 | System and method of allocating storage of devices | Shyamkumar T. Iyer | 2019-10-22 |
| 10395750 | System and method for post-package repair across DRAM banks and bank groups | Stuart Allen Berke | 2019-08-27 |
| 10289339 | System and method for storing modified data to an NVDIMM during a save operation | John E. Jenne, Quy N. Hoang | 2019-05-14 |
| 10229018 | System and method for data restore flexibility on dual channel NVDIMMs | Bhyrav M. Mutnury, Stuart Allen Berke | 2019-03-12 |