Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11080124 | System and method for targeted efficient logging of memory failures | Mark Dykstra, Yuwei Cai | 2021-08-03 |
| 10854242 | Intelligent dual inline memory module thermal controls for maximum uptime | Hasnain Shabbir, Vadhiraj Sankaranarayanan, Mark Dykstra | 2020-12-01 |
| 10761919 | System and method to control memory failure handling on double-data rate dual in-line memory modules | Rene Franco, Tuyet-Huong Thi Nguyen, Vijay Nijhawan, Vadhiraj Sankaranarayanan, Mark L. Farley +1 more | 2020-09-01 |
| 10725671 | Dual inline memory provisioning and reliability, availability, and serviceability enablement based on post package repair history | Ananya Mukherjee, Mark L. Farley, Vadhiraj Sankaranarayanan | 2020-07-28 |
| 10705901 | System and method to control memory failure handling on double-data rate dual in-line memory modules via suspension of the collection of correctable read errors | Tuyet-Huong Thi Nguyen, James R. Pledge, Vadhiraj Sankaranarayanan | 2020-07-07 |
| 6895525 | Method and system for detecting phase-locked loop (PLL) clock synthesis faults | Bruce J. Wilkie | 2005-05-17 |
| 5805836 | Method and apparatus for equalizing grants of a data bus to primary and secondary devices | Steven Russell Barnhart, Kenneth L. Ward | 1998-09-08 |