Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10042647 | Managing a divided load reorder queue | Richard J. Eickemeyer, David A. Hrusecky, Elizabeth A. McGlone, Brian W. Thompto | 2018-08-07 |
| 9977678 | Reconfigurable parallel execution and load-store slice processor | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti +1 more | 2018-05-22 |
| 9971602 | Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti +1 more | 2018-05-15 |
| 9798549 | Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction | Maarten J. Boersma, Robert A. Cordes, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto +1 more | 2017-10-24 |
| 9690586 | Processing of multiple instruction streams in a parallel slice processor | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti +1 more | 2017-06-27 |
| 9690585 | Parallel slice processor with dynamic instruction stream mapping | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti +1 more | 2017-06-27 |
| 9672043 | Processing of multiple instruction streams in a parallel slice processor | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti +1 more | 2017-06-06 |
| 9665372 | Parallel slice processor with dynamic instruction stream mapping | Lee Evan Eisen, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Bruce Joseph Ronchetti +1 more | 2017-05-30 |
| 9519502 | Virtual machine backup | Guy L. Guthrie, Naresh Nayar, Geraint North, William J. Starke | 2016-12-13 |
| 8200946 | Issue unit for placing a processor into a gradual slow mode of operation | Christopher M. Abernathy, Kurt A. Feiste, Ronald P. Hall | 2012-06-12 |
| 8131976 | Tracking effective addresses in an out-of-order processor | Richard W. Doing, Susan E. Eisen, David S. Levitan, Kevin N. Magill, Brian R. Mestan +3 more | 2012-03-06 |
| 8082423 | Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates | Christopher M. Abernathy, Kurt A. Feiste, David Scott Ray, David Shippy | 2011-12-20 |
| 8051315 | Power throttling apparatus | James Allan Kahle, David Shippy | 2011-11-01 |
| 8028151 | Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall | 2011-09-27 |
| 7953960 | Method and apparatus for delaying a load miss flush until issuing the dependent instruction | Kurt A. Feiste, David Scott Ray, David Shippy | 2011-05-31 |
| 7900027 | Scalable link stack control method with full support for speculative operations | Ronald P. Hall, Michael L. Karm, David Mui | 2011-03-01 |
| 7818544 | Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition | Christopher M. Abernathy, Kurt A. Feiste, Ronald P. Hall | 2010-10-19 |
| 7605612 | Techniques for reducing power requirements of an integrated circuit | Owen Chiang, Christopher McCall Durham, Peter Juergen Klim, Daniel Stasiak | 2009-10-20 |
| 7496776 | Power throttling method and apparatus | James Allan Kahle, David Shippy | 2009-02-24 |
| 7475232 | Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines | Christopher M. Abernathy, Jonathan James DeMent, Ronald P. Hall | 2009-01-06 |
| 7437539 | Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline | Christopher M. Abernathy, Kurt A. Feiste, Ronald P. Hall | 2008-10-14 |
| 7434033 | Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline | Christopher M. Abernathy, Kurt A. Feiste, Ronald P. Hall | 2008-10-07 |
| 7313673 | Fine grained multi-thread dispatch block mechanism | Christopher M. Abernathy, Jonathan James DeMent, David Shippy | 2007-12-25 |
| 6792524 | System and method cancelling a speculative branch | Milford John Peterson, David A. Schroter | 2004-09-14 |
| 5446913 | Method and system for nonsequential execution of intermixed scalar and vector instructions in a data processing system utilizing a finish instruction array | Norman C. Chou, Edward J. D'Avignon, James C. Gregerson, James R. Robinson, Michael S. Siegel +1 more | 1995-08-29 |