Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11561901 | Distribution of injected data among caches of a data processing system | Derek E. Williams, Guy L. Guthrie, Bernard C. Drerup, Hugh Shen, Alexander Michael Taft +1 more | 2023-01-24 |
| 9208027 | Address error detection | — | 2015-12-08 |
| 9170639 | Method and apparatus for mitigating effects of memory scrub operations on idle time power savings modes | Joab D. Henderson, Stephen J. Powell, Kenneth L. Wright | 2015-10-27 |
| 8949694 | Address error detection | — | 2015-02-03 |
| 8397029 | System and method for cache coherency in a multiprocessor system | Jason A. Cox, Robert J. Dorsey, Hien Minh Le, Eric F. Robinson, Thuong Quang Truong | 2013-03-12 |
| 8296520 | System and method for optimizing neighboring cache usage in a multiprocessor environment | Hien Minh Le, Jason A. Cox, Robert J. Dorsey, Eric F. Robinson, Thuong Quang Truong | 2012-10-23 |
| 8150672 | Structure for improved logic simulation using a negative unknown boolean state | — | 2012-04-03 |
| 8131974 | Access speculation predictor implemented via idle command processing resources | Ram Raghavan, Eric E. Retter, Jeffrey A. Stuecheli | 2012-03-06 |
| 8127106 | Access speculation predictor with predictions based on a domain indicator of a cache line | Eric E. Retter, Jeffrey A. Stuecheli | 2012-02-28 |
| 8122222 | Access speculation predictor with predictions based on a scope predictor | Eric E. Retter, Jeffrey A. Stuecheli | 2012-02-21 |
| 8122223 | Access speculation predictor with predictions based on memory region prior requestor tag information | Jason F. Cantin, Eric E. Retter, Jeffrey A. Stuecheli | 2012-02-21 |
| 8099570 | Methods, systems, and computer program products for dynamic selective memory mirroring | James A. O'Connor, Kanwal Bahri, Daniel James Henderson, Luis A. Lastras-Montano, Warren E. Maule +6 more | 2012-01-17 |
| 7987437 | Structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization | Bernard C. Drerup | 2011-07-26 |
| 7865644 | Method and apparatus for attaching multiple slave devices to a single bus controller interface while supporting command pipelining | Bernard C. Drerup, Prasanna Srinivasan | 2011-01-04 |
| 7836257 | System and method for cache line replacement selection in a multiprocessor environment | Robert J. Dorsey, Jason A. Cox, Hien Minh Le, Eric F. Robinson, Thuong Quang Truong | 2010-11-16 |
| 7761277 | System and method for improved logic simulation using a negative unknown boolean state | — | 2010-07-20 |
| 7668996 | Method of piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization | Bernard C. Drerup | 2010-02-23 |
| 7620749 | Descriptor prefetch mechanism for high latency and out of order DMA device | Giora Biran, Luis de la Torre, Bernard C. Drerup, Jyoti Gupta | 2009-11-17 |
| 7603490 | Barrier and interrupt mechanism for high latency and out of order DMA device | Giora Biran, Luis de la Torre, Bernard C. Drerup, Jyoti Gupta | 2009-10-13 |
| 7523228 | Method for performing a direct memory access block move in a direct memory access device | Giora Biran, Luis de la Torre, Bernard C. Drerup, Jyoti Gupta | 2009-04-21 |
| 7490201 | Method and bus prefetching mechanism for implementing enhanced buffer control | Bernard C. Drerup, Barry Joe Wolford | 2009-02-10 |
| 7487276 | Bus arbitration system | — | 2009-02-03 |
| 7366811 | Bus arbitration system | — | 2008-04-29 |
| 7328312 | Method and bus prefetching mechanism for implementing enhanced buffer control | Bernard C. Drerup, Barry Joe Wolford | 2008-02-05 |
| 7275199 | Method and apparatus for a modified parity check | Robert C. Dixon, Kirk E. Morrow | 2007-09-25 |