Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10592116 | Load stall interrupt | Charles Ray Johns, Michael J. Neuling, James Xenidis | 2020-03-17 |
| 9971516 | Load stall interrupt | Charles Ray Johns, Michael J. Neuling, James Xenidis | 2018-05-15 |
| 8086977 | Design Structure for switching digital circuit clock net driver without losing clock pulses | Jethro C. Law, John C. Schiff, Glen A. Wiedemeier | 2011-12-27 |
| 7915884 | Importation of virtual signals into electronic test equipment to facilitate testing of an electronic component | Parag Birmiwal, Robert C. Dixon, Hien Minh Le | 2011-03-29 |
| 7752480 | System and method for switching digital circuit clock net driver without losing clock pulses | Jethro C. Law, John C. Schiff, Glen A. Wiedemeier | 2010-07-06 |
| 7742357 | Securing an integrated circuit | Robert C. Dixon, Phil C. Paone | 2010-06-22 |
| 7486585 | Securing an integrated circuit | Robert C. Dixon, Phil C. Paone | 2009-02-03 |
| 7408336 | Importation of virtual signals into electronic test equipment to facilitate testing of an electronic component | Parag Birmiwal, Robert C. Dixon, Hien Minh Le | 2008-08-05 |
| 7321522 | Securing an integrated circuit | Robert C. Dixon, Phil C. Paone | 2008-01-22 |
| 7275199 | Method and apparatus for a modified parity check | Robert C. Dixon, Richard Nicholas | 2007-09-25 |
| 7129769 | Method and apparatus for protecting eFuse information | Robert C. Dixon, William Paul Hovis | 2006-10-31 |
| 7080269 | Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains | Yoanna Baumgartner, Sundeep Chadha, Richard Nicholas Iachetta, Jr., Hien Minh Le | 2006-07-18 |
| 6993470 | Method of evaluating test cases in a simulation environment by harvesting | Yoanna Baumgartner, Maureen Davis, Joseph D. Gerwels | 2006-01-31 |