Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11662765 | System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfaces | Mahalingam Nagarajan, Vaishnav Srinivas, Christophe Avoinne, Michael Jäger | 2023-05-30 |
| 11372717 | Memory with system ECC | Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Laurent Moll | 2022-06-28 |
| 11295803 | Memory with dynamic voltage scaling | Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Laurent Moll | 2022-04-05 |
| 9098658 | Display and automatic improvement of timing and area in a network-on-chip | Daniel Michel, Xavier Van Ruymbeke, Pascal Godet | 2015-08-04 |
| 8793644 | Display and automatic improvement of timing and area in a network-on-chip | Daniel Michel, Xavier Van Ruymbeke, Pascal Godet | 2014-07-29 |