Issued Patents All Time
Showing 25 most recent of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12340859 | Hybrid memory system with increased bandwidth | — | 2025-06-24 |
| 12307092 | Reducing latency in pseudo channel based memory systems | Shyamkumar Thoziyoor, Pankaj Deshmukh, Subbarao Palacharla | 2025-05-20 |
| 12299283 | Self-characterizing, evaluating, and adaptive high performance memory controller | Pankaj Deshmukh, Subbarao Palacharla, Shyamkumar Thoziyoor, Anurag Nannaka | 2025-05-13 |
| 12230347 | System and memory with configurable metadata portion | Dexter Tamio Chun, Anand Srinivasan, Olivier Alavoine, Laurent Moll | 2025-02-18 |
| 12159033 | Metadata registers for a memory device | Pankaj Deshmukh, Michael Hawjing Lo, Subbarao Palacharla, Olivier Alavoine | 2024-12-03 |
| 12153531 | Multiple-core memory controller | Pankaj Deshmukh, Shyamkumar Thoziyoor, Vishakh Balakuntalam Visweswara, Subbarao Palacharla | 2024-11-26 |
| 12073901 | Hybrid memory system with increased bandwidth | — | 2024-08-27 |
| 12038855 | Memory system with adaptive refresh | Pankaj Deshmukh, Shyamkumar Thoziyoor, Vishakh Balakuntalam Visweswara, Subbarao Palacharla | 2024-07-16 |
| 11907141 | Flexible dual ranks memory system to boost performance | Pankaj Deshmukh, Shyamkumar Thoziyoor, Subbarao Palacharla | 2024-02-20 |
| 11893240 | Reducing latency in pseudo channel based memory systems | Shyamkumar Thoziyoor, Pankaj Deshmukh, Subbarao Palacharla | 2024-02-06 |
| 11823762 | Low power memory system using dual input-output voltage supplies | Joon Young Park, Mahalingam Nagarajan | 2023-11-21 |
| 11728003 | System and memory with configurable error-correction code (ECC) data protection and related methods | Dexter Tamio Chun, Anand Srinivasan, Olivier Alavoine, Laurent Moll | 2023-08-15 |
| 11662919 | Enhanced data clock operations in memory | Dexter Tamio Chun, Michael Hawjing Lo, Shyamkumar Thoziyoor, Ravindra Kumar | 2023-05-30 |
| 11631450 | Partial refresh technique to save memory refresh power | Yanru Li, Michael Hawjing Lo, Dexter Tamio Chun | 2023-04-18 |
| 11551730 | Low power memory system using dual input-output voltage supplies | Joon Young Park, Mahalingam Nagarajan | 2023-01-10 |
| 11372717 | Memory with system ECC | Michael Hawjing Lo, Dexter Tamio Chun, Xavier Leloup, Laurent Moll | 2022-06-28 |
| 11360897 | Adaptive memory access management | Pankaj Deshmukh, Michael Hawjing Lo, Shyamkumar Thoziyoor | 2022-06-14 |
| 11295803 | Memory with dynamic voltage scaling | Michael Hawjing Lo, Dexter Tamio Chun, Xavier Leloup, Laurent Moll | 2022-04-05 |
| 11281526 | Optimized error-correcting code (ECC) for data protection | Alain Artieri, Deepti Vijayalakshmi Sriramagiri, Dexter Tamio Chun | 2022-03-22 |
| 11175836 | Enhanced data clock operations in memory | Dexter Tamio Chun, Michael Hawjing Lo, Shyamkumar Thoziyoor, Ravindra Kumar | 2021-11-16 |
| 11164618 | Partial refresh technique to save memory refresh power | Yanru Li, Michael Hawjing Lo, Dexter Tamio Chun | 2021-11-02 |
| 11024361 | Coincident memory bank access via cross connected shared bank resources | Yanru Li, Dexter Tamio Chun | 2021-06-01 |
| 10922168 | Dynamic link error protection in memory systems | Alain Artieri, Dexter Tamio Chun, Deepti Vijayalakshmi Sriramagiri | 2021-02-16 |
| 10853163 | Optimized error-correcting code (ECC) for data protection | Alain Artieri, Deepti Vijayalakshmi Sriramagiri, Dexter Tamio Chun | 2020-12-01 |
| 10852809 | Power saving techniques for memory systems by consolidating data in data lanes of a memory bus | Dexter Tamio Chun, Michael Hawjing Lo | 2020-12-01 |