Issued Patents All Time
Showing 26–50 of 89 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10726904 | Partial refresh technique to save memory refresh power | Yanru Li, Michael Hawjing Lo, Dexter Tamio Chun | 2020-07-28 |
| 10409540 | Electronic device including a plurality of touch displays and method for changing status thereof | Kwangik Cho | 2019-09-10 |
| 10394724 | Low power data transfer for memory subsystem using data pattern checker to determine when to suppress transfers based on specific patterns | Dexter Tamio Chun, Haw-Jing Lo | 2019-08-27 |
| 10393544 | Method for performing function using sensor data and electronic device for providing same | Dohyoung CHUNG, Jeongmin PARK, Donghwan Bae, Cheoljun Lee, Jeongho Cho +2 more | 2019-08-27 |
| 10387242 | Dynamic link error protection in memory systems | Alain Artieri, Dexter Tamio Chun, Deepti Vijayalakshmi Sriramagiri | 2019-08-20 |
| 10332582 | Partial refresh technique to save memory refresh power | Yanru Li, Michael Hawjing Lo, Dexter Tamio Chun | 2019-06-25 |
| 10331517 | Link error correction in memory system | — | 2019-06-25 |
| 10222853 | Power saving techniques for memory systems by consolidating data in data lanes of a memory bus | Dexter Tamio Chun, Michael Hawjing Lo | 2019-03-05 |
| 10185515 | Unified memory controller for heterogeneous memory on a multi-chip package | Hyunsuk Shin, Jung Pill Kim, Dexter Tamio Chun | 2019-01-22 |
| 10169262 | Low-power clocking for a high-speed memory interface | David Ian West, Vaishnav Srinivas, Michael Brunolli | 2019-01-01 |
| 10140175 | Protecting an ECC location when transmitting correction data across a memory link | David Ian West | 2018-11-27 |
| 10061645 | Memory array and link error correction in a low power memory sub-system | David Ian West | 2018-08-28 |
| 9965352 | Separate link and array error correction in a memory system | David Ian West | 2018-05-08 |
| 9911485 | Method and apparatus for refreshing a memory cell | Deepti Vijayalakshmi Sriramagiri, Jung Pill Kim, Xiangyu Dong | 2018-03-06 |
| 9812222 | Method and apparatus for in-system management and repair of semi-conductor memory failure | Jung Pill Kim, Dexter Tamio Chun, Deepti Vijayalakshmi Sriramagiri, Yanru Li, Mosaddiq Saifuddin +1 more | 2017-11-07 |
| 9779798 | Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array | Yanru Li, Dexter Tamio Chun, Alexander Gantman | 2017-10-03 |
| 9766092 | Method for performing function using sensor data and electronic device for providing same | Dohyoung CHUNG, Jeongmin PARK, Donghwan Bae, Cheoljun Lee, Jeongho Cho +2 more | 2017-09-19 |
| 9704557 | Method and apparatus for storing retention time profile information based on retention time and temperature | Xiangyu Dong, Jung Pill Kim, Deepti Vijayalakshmi Sriramagiri | 2017-07-11 |
| 9633698 | Dynamic control of signaling power based on an error rate | Dexter Tamio Chun, Vaishnav Srinivas, David Ian West, Deepti Vijayalakshmi Sriramagiri, Jason Thurston | 2017-04-25 |
| 9583219 | Method and apparatus for in-system repair of memory in burst refresh | Jung Pill Kim, Dexter Tamio Chun, Deepti Vijayalakshmi Sriramagiri | 2017-02-28 |
| 9524771 | DRAM sub-array level autonomic refresh memory controller optimization | Deepti Vijayalakshmi Sriramagiri, Xiangyu Dong | 2016-12-20 |
| 9495261 | Systems and methods for reducing memory failures | Jung Pill Kim, Dexter Tamio Chun, Deepti Vijayalakshmi Sriramagiri, Mosaddiq Saifuddin, Xiangyu Dong +2 more | 2016-11-15 |
| 9448947 | Inter-chip memory interface structure | Dexter Tamio Chun | 2016-09-20 |
| 9436606 | System and method to defragment a memory | Xiangyu Dong | 2016-09-06 |
| 9411727 | Split write operation for resistive memory cache | Xiangyu Dong, Xiaochun Zhu | 2016-08-09 |