Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11281526 | Optimized error-correcting code (ECC) for data protection | Alain Artieri, Dexter Tamio Chun, Jungwon Suh | 2022-03-22 |
| 10922168 | Dynamic link error protection in memory systems | Jungwon Suh, Alain Artieri, Dexter Tamio Chun | 2021-02-16 |
| 10853163 | Optimized error-correcting code (ECC) for data protection | Alain Artieri, Dexter Tamio Chun, Jungwon Suh | 2020-12-01 |
| 10387242 | Dynamic link error protection in memory systems | Jungwon Suh, Alain Artieri, Dexter Tamio Chun | 2019-08-20 |
| 9911485 | Method and apparatus for refreshing a memory cell | Jung Pill Kim, Jungwon Suh, Xiangyu Dong | 2018-03-06 |
| 9812222 | Method and apparatus for in-system management and repair of semi-conductor memory failure | Jung Pill Kim, Dexter Tamio Chun, Jungwon Suh, Yanru Li, Mosaddiq Saifuddin +1 more | 2017-11-07 |
| 9704557 | Method and apparatus for storing retention time profile information based on retention time and temperature | Xiangyu Dong, Jung Pill Kim, Jungwon Suh | 2017-07-11 |
| 9633698 | Dynamic control of signaling power based on an error rate | Dexter Tamio Chun, Vaishnav Srinivas, David Ian West, Jungwon Suh, Jason Thurston | 2017-04-25 |
| 9583219 | Method and apparatus for in-system repair of memory in burst refresh | Jung Pill Kim, Dexter Tamio Chun, Jungwon Suh | 2017-02-28 |
| 9524771 | DRAM sub-array level autonomic refresh memory controller optimization | Jungwon Suh, Xiangyu Dong | 2016-12-20 |
| 9507675 | Systems and methods for recovering from uncorrected DRAM bit errors | Dexter Tamio Chun, Yanru Li, Jung Pill Kim | 2016-11-29 |
| 9495261 | Systems and methods for reducing memory failures | Jung Pill Kim, Dexter Tamio Chun, Mosaddiq Saifuddin, Xiangyu Dong, Sungryul Kim +2 more | 2016-11-15 |
| 9437278 | Low latency synchronization scheme for mesochronous DDR system | Edwin Jose, Michael Drop, Xuhao Huang, Raghu Sankuratri, Marzio Pedrali-Noy | 2016-09-06 |
| 9299457 | Kernel masking of DRAM defects | Dexter Tamio Chun, Yanru Li, Xiangyu Dong, Jungwon Suh, Jung Pill Kim | 2016-03-29 |
| 9123408 | Low latency synchronization scheme for mesochronous DDR system | Edwin Jose, Michael Drop, Xuhao Huang, Raghu Sankuratri, Marzio Pedrali-Noy | 2015-09-01 |
| 8347020 | Memory access controller, systems, and methods for optimizing memory access times | Srinivas Maddali | 2013-01-01 |