Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10642337 | Active power management in a computing device subsystem based on micro-idle duration | Vinod Chamarty, Trang T. Nguyen, Edwin Jose, Xin Kang, Sean D. Sweeney +2 more | 2020-05-05 |
| 9875785 | Refresh timer synchronization between memory controller and memory | Edwin Jose | 2018-01-23 |
| 9734878 | Systems and methods for individually configuring dynamic random access memories sharing a common command access bus | Farrukh Aquil, Vaishnav Srinivas, Philip Michael Clovis | 2017-08-15 |
| 9734890 | Systems and methods for individually configuring dynamic random access memories sharing a common command access bus | Farrukh Aquil, Vaishnav Srinivas, Philip Michael Clovis | 2017-08-15 |
| 9705620 | Synchronization of endpoints using tunable latency | Philip Michael Clovis, Isaac Berk | 2017-07-11 |
| 9632562 | Systems and methods for reducing volatile memory standby power in a portable computing device | Nhon Quach, Virat Deepak, Oscar Cabral Arias, Yanru Li, Haw-Jing Lo +2 more | 2017-04-25 |
| 9437278 | Low latency synchronization scheme for mesochronous DDR system | Edwin Jose, Xuhao Huang, Raghu Sankuratri, Deepti Vijayalakshmi Sriramagiri, Marzio Pedrali-Noy | 2016-09-06 |
| 9396109 | Method and apparatus for DRAM spatial coalescing within a single channel | Dexter Tamio Chun, Haw-Jing Lo | 2016-07-19 |
| 9123408 | Low latency synchronization scheme for mesochronous DDR system | Edwin Jose, Xuhao Huang, Raghu Sankuratri, Deepti Vijayalakshmi Sriramagiri, Marzio Pedrali-Noy | 2015-09-01 |
| 9086877 | System and method of monitoring a central processing unit in real time | Steven S. Thomson, Ali Iranli, Vinodh R. Cuppu, Christopher Kong Yee Chun, Tao Xue +2 more | 2015-07-21 |
| 8352759 | System and method of monitoring a central processing unit in real time | Steven S. Thomson, Ali Iranli, Vinodh R. Cuppu, Christopher Kong Yee Chun, Tao Xue +2 more | 2013-01-08 |
| 8098539 | Hybrid single and dual channel DDR interface scheme by interleaving address/control signals during dual channel operation | Raghu Sankuratri, Jian Mao | 2012-01-17 |
| 7437580 | Dynamic voltage scaling system | Eric L. Henderson, Tauseef Kazi | 2008-10-14 |