| 12307092 |
Reducing latency in pseudo channel based memory systems |
Pankaj Deshmukh, Jungwon Suh, Subbarao Palacharla |
2025-05-20 |
| 12299283 |
Self-characterizing, evaluating, and adaptive high performance memory controller |
Pankaj Deshmukh, Subbarao Palacharla, Jungwon Suh, Anurag Nannaka |
2025-05-13 |
| 12153531 |
Multiple-core memory controller |
Pankaj Deshmukh, Vishakh Balakuntalam Visweswara, Jungwon Suh, Subbarao Palacharla |
2024-11-26 |
| 12038855 |
Memory system with adaptive refresh |
Pankaj Deshmukh, Vishakh Balakuntalam Visweswara, Jungwon Suh, Subbarao Palacharla |
2024-07-16 |
| 11907141 |
Flexible dual ranks memory system to boost performance |
Jungwon Suh, Pankaj Deshmukh, Subbarao Palacharla |
2024-02-20 |
| 11893240 |
Reducing latency in pseudo channel based memory systems |
Pankaj Deshmukh, Jungwon Suh, Subbarao Palacharla |
2024-02-06 |
| 11662919 |
Enhanced data clock operations in memory |
Jungwon Suh, Dexter Tamio Chun, Michael Hawjing Lo, Ravindra Kumar |
2023-05-30 |
| 11520706 |
Dram-aware caching |
Alain Artieri, Rakesh Gupta, Subbarao Palacharla, Kedar Bhole, Laurent Moll +8 more |
2022-12-06 |
| 11403217 |
Memory bank group interleaving |
Alain Artieri, Jean-Jacques Lecler |
2022-08-02 |
| 11360897 |
Adaptive memory access management |
Jungwon Suh, Pankaj Deshmukh, Michael Hawjing Lo |
2022-06-14 |
| 11175836 |
Enhanced data clock operations in memory |
Jungwon Suh, Dexter Tamio Chun, Michael Hawjing Lo, Ravindra Kumar |
2021-11-16 |
| 8495537 |
Timing analysis of an array circuit cross section |
Tae Hong Kim, Sang-Yeol Lee |
2013-07-23 |
