Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Power disconnect unit for use in data transport topology of network on chip design having asynchronous clock domain adapter sender and receiver each at a separate power domain

Power disconnect unit for use in data transport topology of network on chip design having asynchronous clock domain adapter sender and receiver each at a separate power domain

US Patent 9177615 · Granted Nov 3, 2015

Estimated economic value: $4,381,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Data routing for networks on a chip using virtual channels and credit restrictio2025
Method and apparatus for exclusive access fairness in memory systems with distri2025
Encoding byte information on a data bus with separate code2024
Coherent interconnect power reduction using hardware controlled split snoop dire2020
Zero-latency network on chip (NoC)2018
Tunneling within a network-on-chip topology2017
Network on a chip socket protocol2016
DMA engine with STLB prefetch capabilities and tethered prefetching2016
System translation look-aside buffer integrated in an interconnect2016
Network on a chip socket protocol2015
Method and device for managing priority during the transmission of a message2015
System translation look-aside buffer with request-based allocation and prefetchi2015