Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Zero-latency network on chip (NoC)

Zero-latency network on chip (NoC)

US Patent 9882839 · Granted Jan 30, 2018

Estimated economic value: $9,727,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Data routing for networks on a chip using virtual channels and credit restrictio2025
Method and apparatus for exclusive access fairness in memory systems with distri2025
Encoding byte information on a data bus with separate code2024
Dram-aware caching2022
Memory bank group interleaving2022
Dynamic memory scheduling routine with enhanced bank-group batching2021
Method and apparatus for ternary mapping2021
Coherent interconnect power reduction using hardware controlled split snoop dire2020
Coherency controller with reduced data buffer2017
Tunneling within a network-on-chip topology2017
Adaptive tuning of snoops2017
Differential formatting between normal and retry data transmission2016