Eric Norige — 39 Patents at Netspeed Systems

Eric Norige has been granted 39 US patents while listed as an inventor at Netspeed Systems. The first was granted in 2013 and the most recent in June 2025. Eric Norige ranks #81,245 of 4,157,543 US inventors in our database (top 2.0%). Patent records list Eric Norige in Santa Clara, CA, US.

Issued Patents All Time

Showing 1–25 of 39 patents

Patent #	Title	Co-Inventors	Date
12332309	Built-in self-test for network on chip fabric	Dawn Maxon, Joji Philip, William John Bainbridge, Joseph B. Rowlands	2025-06-17
10554496	Heterogeneous SoC IP core placement in an interconnect to optimize latency and interconnect performance	Sailesh Kumar	2020-02-04
10528682	Automatic performance characterization of a network-on-chip (NOC) interconnect	Sailesh Kumar, Pier Giorgio Raponi	2020-01-07
10523599	Buffer sizing of a NoC through machine learning	Nishant Rao, Sailesh Kumar	2019-12-31
10496770	System level simulation in Network on Chip architecture	Sailesh Kumar, Amit Patankar	2019-12-03
10469338	Cost management against requirements for the generation of a NoC	William John Bainbridge, Sailesh Kumar, Nishant Rao	2019-11-05
10469337	Cost management against requirements for the generation of a NoC	William John Bainbridge, Sailesh Kumar, Nishant Rao	2019-11-05
10419300	Cost management against requirements for the generation of a NoC	William John Bainbridge, Sailesh Kumar, Nishant Rao	2019-09-17
10355996	Heterogeneous channel capacities in an interconnect	Sailesh Kumar, Joji Philip, Sundari Mitra	2019-07-16
10218581	Generation of network-on-chip layout based on user specified topological constraints	Pier Giorgio Raponi, Sailesh Kumar	2019-02-26
10063496	Buffer sizing of a NoC through machine learning	Nishant Rao, Sailesh Kumar	2018-08-28
10050843	Generation of network-on-chip layout based on user specified topological constraints	Pier Giorgio Raponi, Sailesh Kumar	2018-08-14
9928204	Transaction expansion for NoC simulation and NoC design	Sailesh Kumar	2018-03-27
9864728	Automatic generation of physically aware aggregation/distribution networks	Sailesh Kumar	2018-01-09
9781043	Identification of internal dependencies within system components for evaluating potential protocol level deadlocks	Sailesh Kumar, Joji Philip, Joseph B. Rowlands	2017-10-03
9774498	Hierarchical asymmetric mesh with virtual routers	Sailesh Kumar, Joji Philip, Mahmud-Ul Hassan, Sundari Mitra, Joseph B. Rowlands	2017-09-26
9762474	Systems and methods for selecting a router to connect a bridge in the network on chip (NoC)	Sailesh Kumar, Pier Giorgio Raponi	2017-09-12
9590813	Supporting multicast in NoC interconnect	Sailesh Kumar, Joe Rowlands, Joji Philip	2017-03-07
9571402	Congestion control and QoS in NoC by regulating the injection traffic	Sailesh Kumar	2017-02-14
9529400	Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements	Sailesh Kumar, Pier Giorgio Raponi	2016-12-27
9473359	Transactional traffic specification for network-on-chip design	Sailesh Kumar, Pier Giorgio Raponi	2016-10-18
9473388	Supporting multicast in NOC interconnect	Sailesh Kumar, Joe Rowlands, Joji Philip	2016-10-18
9471726	System level simulation in network on chip architecture	Sailesh Kumar, Amit Patankar	2016-10-18
9444702	System and method for visualization of NoC performance based on simulation output	Pier Giorgio Raponi, Sailesh Kumar	2016-09-13
9253085	Hierarchical asymmetric mesh with virtual routers	Sailesh Kumar, Joji Philip, Mahmud-Ul Hassan, Sundari Mitra, Joseph B. Rowlands	2016-02-02

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Eric Norige — 39 Patents

Issued Patents All Time

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