Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System level simulation in network on chip architecture

System level simulation in network on chip architecture

US Patent 9471726 · Granted Oct 18, 2016

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Built-in self-test for network on chip fabric2025
Application mapping on hardened network-on-chip (NoC) of field-programmable gate2025
Flexible on-die fabric interface2024
Vehicle interior component having a composite structure providing a user interfa2023
Flexible on-die fabric interface2023
Systems and methods for use in providing payment transaction notifications2023
System on chip (SoC) builder2021
Method and system for electronic distribution of controlled tokens2021
Application mapping on hardened network-on-chip (NoC) of field-programmable gate2021
Vehicle interior component2021
Repository of integration description of hardware intellectual property for NoC 2021
Interface virtualization and fast path for Network on Chip2020