Issued Patents All Time
Showing 26–50 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7991922 | System on a chip for networking | Mark D. Hayter, James Y. Cho | 2011-08-02 |
| 7987342 | Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer | Richard Win Thaik, John G. Favor, Leonard Eric Shar | 2011-07-26 |
| 7966479 | Concurrent vs. low power branch prediction | Richard Win Thaik, John G. Favor, Leonard Eric Shar | 2011-06-21 |
| 7953933 | Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit | Richard Win Thaik, John G. Favor, Leonard Eric Shar | 2011-05-31 |
| 7953961 | Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder | Richard Win Thaik, John G. Favor, Leonard Eric Shar | 2011-05-31 |
| 7949854 | Trace unit with a trace builder | Richard Win Thaik, John G. Favor, Leonard Eric Shar | 2011-05-24 |
| 7941607 | Method and system for promoting traces in an instruction processing circuit | Richard Win Thaik, John G. Favor, Leonard Eric Shar, Matthew William Ashcraft | 2011-05-10 |
| 7937564 | Emit vector optimization of a trace | Matthew William Ashcraft, John G. Favor, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Richard Win Thaik | 2011-05-03 |
| 7934054 | Re-fetching cache memory enabling alternative operational modes | Laurent Moll, Peter N. Glaskowsky | 2011-04-26 |
| 7877630 | Trace based rollback of a speculatively updated cache | John G. Favor, Paul G. Chan, Graham Ricketson Murphy | 2011-01-25 |
| 7873788 | Re-fetching cache memory having coherent re-fetching | Laurent Moll, Peter N. Glaskowsky | 2011-01-18 |
| 7849292 | Flag optimization of a trace | Matthew William Ashcraft, John G. Favor, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Richard Win Thaik | 2010-12-07 |
| 7814298 | Promoting and appending traces in an instruction processing circuit based upon a bias value | Richard Win Thaik, John G. Favor, Leonard Eric Shar, Matthew William Ashcraft | 2010-10-12 |
| 7797563 | System and method for conserving power | Laurent Moll | 2010-09-14 |
| 7779307 | Memory ordering queue tightly coupled with a versioning cache circuit | John G. Favor, Paul G. Chan, Graham Ricketson Murphy | 2010-08-17 |
| 7752281 | Bridges performing remote reads and writes as uncacheable coherent operations | — | 2010-07-06 |
| 7663961 | Reduced-power memory with per-sector power/ground control and early address | Laurent Moll, John G. Favor, Daniel Fung | 2010-02-16 |
| 7660931 | System on a chip for networking | Mark D. Hayter, James Y. Cho | 2010-02-09 |
| 7647452 | Re-fetching cache memory enabling low-power modes | Laurent Moll, Peter N. Glaskowsky | 2010-01-12 |
| 7549091 | Hypertransport exception detection and processing | Laurent Moll | 2009-06-16 |
| 7469275 | System having interfaces, switch, and memory bridge for CC-NUMA operation | — | 2008-12-23 |
| 7443759 | Reduced-power memory with per-sector ground control | Laurent Moll, John G. Favor, Daniel Fung | 2008-10-28 |
| 7424561 | Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems | Barton Sano, Laurent Moll, Manu Gulati | 2008-09-09 |
| 7418534 | System on a chip for networking | Mark D. Hayter, James Y. Cho | 2008-08-26 |
| 7343456 | Load-linked/store conditional mechanism in a CC-NUMA system | — | 2008-03-11 |