Issued Patents All Time
Showing 76–100 of 166 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8010745 | Rolling back a speculative update of a non-modifiable cache line | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2011-08-30 |
| 7987342 | Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar | 2011-07-26 |
| 7966479 | Concurrent vs. low power branch prediction | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar | 2011-06-21 |
| 7953933 | Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar | 2011-05-31 |
| 7953961 | Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar | 2011-05-31 |
| 7949854 | Trace unit with a trace builder | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar | 2011-05-24 |
| 7941607 | Method and system for promoting traces in an instruction processing circuit | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar, Matthew William Ashcraft | 2011-05-10 |
| 7937564 | Emit vector optimization of a trace | Matthew William Ashcraft, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Joseph B. Rowlands, Richard Win Thaik | 2011-05-03 |
| 7877630 | Trace based rollback of a speculatively updated cache | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2011-01-25 |
| 7870369 | Abort prioritization in a trace-based processor | Christopher Patrick Nelson, Richard Win Thaik | 2011-01-11 |
| 7856548 | Prediction of data values read from memory by a microprocessor using a dynamic confidence threshold | Chris Nelson, Matthew William Ashcraft | 2010-12-21 |
| 7852846 | Method and apparatus for out-of-order processing of packets | Edmund Chen, Stephan G. Meier | 2010-12-14 |
| 7849292 | Flag optimization of a trace | Matthew William Ashcraft, Christopher Patrick Nelson, Ivan Pavle Radivojevic, Joseph B. Rowlands, Richard Win Thaik | 2010-12-07 |
| 7814298 | Promoting and appending traces in an instruction processing circuit based upon a bias value | Richard Win Thaik, Joseph B. Rowlands, Leonard Eric Shar, Matthew William Ashcraft | 2010-10-12 |
| 7808999 | Method and apparatus for out-of-order processing of packets using linked lists | Edmund Chen, Ruchi Wadhawan, Gregory G. Minshall | 2010-10-05 |
| 7802073 | Virtual core management | Yu Qing Cheng, Carlos Puchol, Seungyoon Peter Song, Peter N. Glaskowsky, Laurent Moll +2 more | 2010-09-21 |
| 7797512 | Virtual core management | Yu Qing Cheng, Peter N. Glaskowsky, Laurent Moll, Carlos Puchol, Seungyoon Peter Song | 2010-09-14 |
| 7797517 | Trace optimization via fusing operations of a target architecture operation set | — | 2010-09-14 |
| 7788473 | Prediction of data values read from memory by a microprocessor using the storage destination of a load operation | Chris Nelson, Matthew William Ashcraft, Seungyoon Peter Song | 2010-08-31 |
| 7783863 | Graceful degradation in a trace-based processor | Christopher Patrick Nelson, Richard Win Thaik, Matthew William Ashcraft | 2010-08-24 |
| 7779307 | Memory ordering queue tightly coupled with a versioning cache circuit | Paul G. Chan, Graham Ricketson Murphy, Joseph B. Rowlands | 2010-08-17 |
| 7747822 | Maintaining memory coherency with a trace cache | Richard Win Thaik | 2010-06-29 |
| 7681019 | Executing functions determined via a collection of operations from translated instructions | — | 2010-03-16 |
| 7673122 | Software hint to specify the preferred branch prediction to use for a branch instruction | Seungyoon Peter Song, Richard Win Thaik | 2010-03-02 |
| 7663961 | Reduced-power memory with per-sector power/ground control and early address | Joseph B. Rowlands, Laurent Moll, Daniel Fung | 2010-02-16 |