Issued Patents All Time
Showing 126–150 of 166 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6161173 | Integration of multi-stage execution units with a scheduler for single-stage execution units | Ravi Krishna, Amos Ben-Meir | 2000-12-12 |
| 6154831 | Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values | John S. Thayer, Gary W. Thome, Frederick Daniel Weber | 2000-11-28 |
| 6141673 | Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions | John S. Thayer, Frederick Daniel Weber | 2000-10-31 |
| 6141742 | Method for reducing number of bits used in storage of instruction address pointer values | — | 2000-10-31 |
| 6093213 | Flexible implementation of a system management mode (SMM) in a processor | Frederick Daniel Weber | 2000-07-25 |
| 6067616 | Branch prediction device with two levels of branch prediction cache | David R. Stiles, Korbin S. Van Dyke | 2000-05-23 |
| 6061521 | Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle | John S. Thayer, Gary W. Thome, Frederick Daniel Weber | 2000-05-09 |
| 6047372 | Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot | John S. Thayer, Brian E. Longhenry, Frederick Daniel Weber | 2000-04-04 |
| 6038657 | Scan chains for out-of-order load/store execution control | Amos Ben-Meir, Warren G. Stapleton, Jeffrey E. Trull, Mark E. Roberts | 2000-03-14 |
| 6009505 | System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot | John S. Thayer, Gary W. Thome, Brian E. Longhenry, Frederick Daniel Weber | 1999-12-28 |
| 5960463 | Cache controller with table walk logic tightly coupled to second level access logic | Puneet Sharma | 1999-09-28 |
| 5926642 | RISC86 instruction set | — | 1999-07-20 |
| 5920713 | Instruction decoder including two-way emulation code branching | — | 1999-07-06 |
| 5920515 | Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device | Imtiaz P. Shaik, Dennis L. Wendell, Benjamin Wong, John C. Holst, Donald A. Draper +1 more | 1999-07-06 |
| 5909572 | System and method for conditionally moving an operand from a source register to a destination register | John S. Thayer, Frederick Daniel Weber | 1999-06-01 |
| 5884059 | Unified multi-function operation scheduler for out-of-order execution in a superscalar processor | Amos Ben-Meir, Warren G. Stapleton | 1999-03-16 |
| 5881265 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, Dale R. Greenley +1 more | 1999-03-09 |
| 5881261 | Processing system that rapidly indentifies first or second operations of selected types for execution | Amos Ben-Meir, Jeffrey E. Trull | 1999-03-09 |
| 5826073 | Self-modifying code handling system | Amos Ben-Meir | 1998-10-20 |
| 5819056 | Instruction buffer organization method and system | — | 1998-10-06 |
| 5809273 | Instruction predecode and multiple instruction decode | Amos Ben-Meir | 1998-09-15 |
| 5801975 | Computer modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instruction cycles | John S. Thayer, Frederick Daniel Weber | 1998-09-01 |
| 5799165 | Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay | Amos Ben-Meir | 1998-08-25 |
| 5794063 | Instruction decoder including emulation using indirect specifiers | — | 1998-08-11 |
| 5781753 | Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, Dale R. Greenley +1 more | 1998-07-14 |