Issued Patents All Time
Showing 151–166 of 166 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5768575 | Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, Dale R. Greenley +1 more | 1998-06-16 |
| 5761736 | Apparatus and method for implementing multiple scaled states in a state machine | Puneet Sharma | 1998-06-02 |
| 5754812 | Out-of-order load/store execution control | Amos Ben-Meir, Warren G. Stapleton, Jeffrey E. Trull, Mark E. Roberts | 1998-05-19 |
| 5748932 | Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence | Korbin S. Van Dyke, David R. Stiles | 1998-05-05 |
| 5745724 | Scan chain for rapidly identifying first or second objects of selected types in a sequential list | Amos Ben-Meir, Jeffrey E. Trull | 1998-04-28 |
| 5682492 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, Dale R. Greenley +1 more | 1997-10-28 |
| 5649137 | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency | Korbin S. Van Dyke, David R. Stiles | 1997-07-15 |
| 5515518 | Two-level branch prediction cache | David R. Stiles, Korbin S. Van Dyke | 1996-05-07 |
| 5511175 | Method an apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency | Korbin S. Van Dyke, David R. Stiles | 1996-04-23 |
| 5442757 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, Dale R. Greenley +1 more | 1995-08-15 |
| 5327547 | Two-level branch prediction cache | David R. Stiles, Korbin S. Van Dyke | 1994-07-05 |
| 5230068 | Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence | Korbin S. Van Dyke, David R. Stiles | 1993-07-20 |
| 5226130 | Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency | Korbin S. Van Dyke, David R. Stiles | 1993-07-06 |
| 5226126 | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, Dale R. Greenley +1 more | 1993-07-06 |
| 5163140 | Two-level branch prediction cache | David R. Stiles, Korbin S. Van Dyke | 1992-11-10 |
| 5093778 | Integrated single structure branch prediction cache | David R. Stiles, Korbin S. Van Dyke, Walstein Bennett Smith, III | 1992-03-03 |