Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6499123 | Method and apparatus for debugging an integrated circuit | David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 2002-12-24 |
| 6212629 | Method and apparatus for executing string instructions | David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 2001-04-03 |
| 5881265 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1999-03-09 |
| 5781753 | Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions | David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1998-07-14 |
| 5768575 | Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions | David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1998-06-16 |
| 5682492 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1997-10-28 |
| 5627976 | Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture | Allen P. Ho | 1997-05-06 |
| 5572159 | Voltage-controlled delay element with programmable delay | — | 1996-11-05 |
| 5442757 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1995-08-15 |
| 5414820 | Crossing transfers for maximizing the effective bandwidth in a dual-bus architecture | Allen P. Ho | 1995-05-09 |
| 5388227 | Transparent data bus sizing | — | 1995-02-07 |
| 5369748 | Bus arbitration in a dual-bus architecture where one bus has relatively high latency | Allen P. Ho | 1994-11-29 |
| 5226126 | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags | David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor, Dale R. Greenley +1 more | 1993-07-06 |
| 5125093 | Interrupt control for multiprocessor computer system | — | 1992-06-23 |
| 4740911 | Dynamically controlled interleaving | Len Shar | 1988-04-26 |
| 4736124 | High speed data bus structure | — | 1988-04-05 |
| 4595923 | Improved terminator for high speed data bus | — | 1986-06-17 |
| 4481625 | High speed data bus system | Allen W. Roberts, Harlan Lau | 1984-11-06 |