Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7472323 | Mechanism to stop instruction execution at a microprocessor | Chitresh Narasimhaiah, Senthilkumar Diraviam | 2008-12-30 |
| 6546531 | Automatic delay element insertion system for addressing holdtime problems | Le Tu Quach, Lakshminarasimhan Varadadesikan | 2003-04-08 |
| 6499123 | Method and apparatus for debugging an integrated circuit | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 2002-12-24 |
| 6212629 | Method and apparatus for executing string instructions | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 2001-04-03 |
| 6185711 | Methods and apparatus for synchronizing asynchronous test structures and eliminating clock skew considerations | Arthur T. Leung | 2001-02-06 |
| 6006312 | Cachability attributes of virtual addresses for optimizing performance of virtually and physically indexed caches in maintaining multiply aliased physical addresses | Leslie D. Kohn, Ken Okin | 1999-12-21 |
| 5920889 | Apparatus and method for write miss processing in a copy-back data cache with an allocating load buffer and a non-allocating store buffer | Bruce E. Petrick | 1999-07-06 |
| 5904732 | Dynamic priority switching of load and store buffers in superscalar processor | Leslie D. Kohn | 1999-05-18 |
| 5881265 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1999-03-09 |
| 5802575 | Hit bit for indicating whether load buffer entries will hit a cache when they reach buffer head | Leslie D. Kohn, Ming-Hsin Yeh, Greg Williams | 1998-09-01 |
| 5781753 | Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1998-07-14 |
| 5768575 | Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1998-06-16 |
| 5761469 | Method and apparatus for optimizing signed and unsigned load processing in a pipelined processor | — | 1998-06-02 |
| 5745729 | Methods and apparatuses for servicing load instructions | Leslie D. Kohn, Ming-Hsin Yeh, Greg Williams | 1998-04-28 |
| 5715425 | Apparatus and method for prefetching data into an external cache | Gary S. Goldman, Bruce E. Petrick, Marc Tremblay | 1998-02-03 |
| 5682492 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1997-10-28 |
| 5442757 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1995-08-15 |
| 5226126 | Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, John G. Favor +1 more | 1993-07-06 |