Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5699551 | Software invalidation in a multiple level, multiple cache system | George S. Taylor, P. Michael Farmwald, Timothy P. Layman, Huy X. Ngo | 1997-12-16 |
| 5542062 | Cache memory system employing virtual address primary instruction and data caches and physical address secondary cache | George S. Taylor, P. Michael Farmwald, Timothy P. Layman, Huy X. Ngo | 1996-07-30 |
| 5307477 | Two-level cache memory system | George S. Taylor, P. Michael Farmwald, Timothy P. Layman, Huy X. Ngo | 1994-04-26 |
| 5056110 | Differential bus with specified default value | Timonty S. Fu | 1991-10-08 |
| 4481625 | High speed data bus system | Harold L. McFarland, Harlan Lau | 1984-11-06 |