PF

P. Michael Farmwald

MS Matrix Semiconductor: 5 patents #21 of 55Top 40%
UT Utstarcom: 3 patents #22 of 185Top 15%
SG Silicon Graphics: 2 patents #198 of 758Top 30%
BL Blackberry Limited: 1 patents #1,631 of 2,554Top 65%
CR Chromatic Research: 1 patents #7 of 18Top 40%
MS Mips Computer Systems: 1 patents #12 of 25Top 50%
Overall (All Time): #324,475 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8908516 Maintaining stability of a wireless network by adjusting transmitting period Assimakis Tzamaloukas 2014-12-09
7376130 System for enhancing data transfer 2008-05-20
7254648 Universal broadband server system and method Timothy Kelliher, Patrick J. Coleman 2007-08-07
7233649 Faster modem method and apparatus Timothy Kelliher 2007-06-19
6867992 Modular memory device J. James Tringali, Thomas H. Lee, Mark G. Johnson, Derek Bosch 2005-03-15
6839343 Physical layer router system and method Timothy Kelliher, Patrick J. Coleman 2005-01-04
6798769 System for enhancing data transfer 2004-09-28
6545891 Modular memory device J. James Tringali, Thomas H. Lee, Mark G. Johnson, Derek Bosch 2003-04-08
6515888 Low cost three-dimensional memory array Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, N. Johan Knall 2003-02-04
6351406 Vertically stacked field programmable nonvolatile memory and method of fabrication Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, James M. Cleeves 2002-02-26
6185122 Vertically stacked field programmable nonvolatile memory and method of fabrication Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, James M. Cleeves 2001-02-06
5712799 Method and structure for performing motion estimation using reduced precision pixel intensity values Stephen C. Purcell, Andrew Hung, Chad Fogg 1998-01-27
5699551 Software invalidation in a multiple level, multiple cache system George S. Taylor, Timothy P. Layman, Huy X. Ngo, Allen W. Roberts 1997-12-16
5542062 Cache memory system employing virtual address primary instruction and data caches and physical address secondary cache George S. Taylor, Timothy P. Layman, Huy X. Ngo, Allen W. Roberts 1996-07-30
5307477 Two-level cache memory system George S. Taylor, Timothy P. Layman, Huy X. Ngo, Allen W. Roberts 1994-04-26