Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
NK

N. Johan Knall — 41 Patents

MSMatrix Semiconductor: 21 patents #4 of 55Top 8%
CTCandescent Technologies: 13 patents #15 of 125Top 15%
S3Sandisk 3D: 6 patents #75 of 180Top 45%
STSandisk Technologies: 1 patents #1,462 of 394Top 375%
Sunnyvale, CA: #474 of 14,302 inventorsTop 4%
California: #11,075 of 386,348 inventorsTop 3%
Overall (All Time): #75,001 of 4,157,543Top 2%
41 Patents All Time
N. Johan Knall has been granted 41 US patents while listed as an inventor at Matrix Semiconductor. The first was granted in 1999 and the most recent in November 2013. N. Johan Knall ranks #75,001 of 4,157,543 US inventors in our database (top 1.8%). Patent records list N. Johan Knall in Sunnyvale, CA, US.

Issued Patents All Time

Showing 1–25 of 41 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8575719 Silicon nitride antifuse for use in diode-antifuse memory arrays Mark G. Johnson, S. Brad Herner 2013-11-05 $10,324,000
7816188 Process for fabricating a dielectric film using plasma oxidation Michael A. Vyvoda, James M. Cleeves 2010-10-19 $9,155,000
7413945 Electrically isolated pillars in active devices Michael A. Vyvoda, Manish Bhatia, James M. Cleeves 2008-08-19 $8,644,000
7304888 Reverse-bias method for writing memory cells in a memory array 2007-12-04 $8,204,000
7245000 Electrically isolated pillars in active devices Michael A. Vyvoda, Manish Bhatia, James M. Cleeves 2007-07-17 $29,931,000
7091529 Three-dimensional memory array and method of fabrication Mark G. Johnson 2006-08-15 $26,307,000
7071565 Patterning three dimensional structures Calvin K. Li, Michael A. Vyvoda, James M. Cleeves, Vivek Subramanian 2006-07-04
7022572 Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells Roy E. Scheuerlein 2006-04-04
6963504 Apparatus and method for disturb-free programming of passive element memory cells Roy E. Scheuerlein 2005-11-08
6954394 Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions Roy E. Scheuerlein, James M. Cleeves, Bendik Kleveland, Mark G. Johnson 2005-10-11
6952043 Electrically isolated pillars in active devices Michael A. Vyvoda, Manish Bhatia, James M. Cleeves 2005-10-04
6888750 Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication Andrew J. Walker, Mark G. Johnson, Igor G. Kouznetsov, Christopher J. Petti 2005-05-03
6822903 Apparatus and method for disturb-free programming of passive element memory cells Roy E. Scheuerlein 2004-11-23
6777773 Memory cell with antifuse layer formed at diode junction 2004-08-17
6770939 Thermal processing for three dimensional circuits Vivek Subramanian, James M. Cleeves, Calvin K. Li, Michael A. Vyvoda 2004-08-03
6768185 Formation of antifuse structure in a three dimensional memory James M. Cleeves, Michael A. Vyvoda 2004-07-27
6767816 Method for making a three-dimensional memory array incorporating serial chain diode stack Bendik Kleveland 2004-07-27
6704235 Anti-fuse memory cell with asymmetric breakdown voltage James M. Cleeves, Igor G. Kouznetsov, Michael A. Vyvoda 2004-03-09
6653712 Three-dimensional memory array and method of fabrication Mark G. Johnson 2003-11-25
6642603 Same conductivity type highly-doped regions for antifuse memory cell 2003-11-04
6631085 Three-dimensional memory array incorporating serial chain diode stack Bendik Kleveland, Roy E. Scheuerlein, Mark G. Johnson, Thomas H. Lee 2003-10-07
6627530 Patterning three dimensional structures Calvin K. Li, Michael A. Vyvoda, James M. Cleeves, Vivek Subramanian 2003-09-30
6624011 Thermal processing for three dimensional circuits Vivek Subramanian, James M. Cleeves, Calvin K. Li, Michael A. Vyvoda 2003-09-23
6541312 Formation of antifuse structure in a three dimensional memory James M. Cleeves, Michael A. Vyvoda 2003-04-01
6515888 Low cost three-dimensional memory array Mark G. Johnson, Thomas H. Lee, Vivek Subramanian, P. Michael Farmwald 2003-02-04