Issued Patents All Time
Showing 25 most recent of 271 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| RE46435 | Three dimensional hexagonal matrix memory array | Christopher J. Petti | 2017-06-13 |
| 9646688 | Three dimensional non-volatile storage with connected word lines | — | 2017-05-09 |
| 9576660 | Low forming voltage non-volatile storage device | Zhida Lan, Tong Zhang, Kun Hou, Perumal Ratnam | 2017-02-21 |
| 9472301 | Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same | Abhijit Bandyopadhyay, Tanmay Kumar, Scott Brad Herner, Christopher J. Petti | 2016-10-18 |
| 9368207 | Method of operating FET low current 3D re-ram | Abhijit Bandyopadhyay, Chandrasekhar Gorla, Brian Le | 2016-06-14 |
| 9269425 | Low forming voltage non-volatile storage device | Zhida Lan, Tong Zhang, Kun Hou, Perumal Ratnam | 2016-02-23 |
| 9245629 | Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines | George Samachisa, Luca Fasoli, Masaaki Higashitani | 2016-01-26 |
| 9202539 | Methods and apparatus for reducing programming time of a memory cell | Tyler Thorp | 2015-12-01 |
| 9171584 | Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines | Chang Hua Siau | 2015-10-27 |
| 9152562 | Storage sub-system for a computer comprising write-once memory devices and write-many memory devices and related method | Randhir P. S. Thakur, Christopher S. Moore | 2015-10-06 |
| 9123392 | Non-volatile 3D memory with cell-selectable word line decoding | Tianhong Yan | 2015-09-01 |
| 9111800 | Floating body memory cell system and method of manufacture | — | 2015-08-18 |
| 9105576 | Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same | Yung-Tin Chen, Andrei Mihnea, Luca Fasoli | 2015-08-11 |
| 9076518 | Three-dimensional memory structures having shared pillar memory cells | Eliyahou Harari | 2015-07-07 |
| 9065044 | Three dimensional non-volatile storage with connected word lines | — | 2015-06-23 |
| 9059401 | Three dimensional non-volatile storage with three device driver for row select | — | 2015-06-16 |
| 9048422 | Three dimensional non-volatile storage with asymmetrical vertical select devices | — | 2015-06-02 |
| 9047983 | Temperature compensation of conductive bridge memory arrays | George Samachisa | 2015-06-02 |
| 9030859 | Three dimensional non-volatile storage with dual layers of select devices | Raul-Adrian Cernea | 2015-05-12 |
| 9006795 | Resistance-switching memory cells adapted for use at low voltage | Xiaoyu Yang, Feng Li, Albert T. Meeks | 2015-04-14 |
| 8995169 | Method of operating FET low current 3D Re-RAM | Abhijit Bandyopadhyay, Chandrasekhar Gorla, Brian Le | 2015-03-31 |
| 8969923 | Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning | Christopher J. Petti, Yoichiro Tanaka | 2015-03-03 |
| 8946017 | Method of making a TFT charge storage memory cell having high-mobility corrugated channel | — | 2015-02-03 |
| 8934292 | Balanced method for programming multi-layer cell memories | Xiying Costa, Yibo Nian, Tz-Yi Liu, Chandrasekhar Gorla | 2015-01-13 |
| 8923050 | 3D memory with vertical bit lines and staircase word lines and vertical switches and methods thereof | Raul-Adrian Cernea | 2014-12-30 |