Issued Patents All Time
Showing 51–75 of 271 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8618614 | Continuous mesh three dimensional non-volatile storage with vertical select devices | — | 2013-12-31 |
| 8619453 | Three dimensional non-volatile storage with dual gate selection of vertical bit lines | — | 2013-12-31 |
| 8605486 | Cross point non-volatile memory cell | — | 2013-12-10 |
| 8576651 | Temperature compensation of conductive bridge memory arrays | George Samachisa | 2013-11-05 |
| 8576609 | Structure and method for biasing phase change memory array for reliable writing | — | 2013-11-05 |
| 8575715 | Punch-through diode steering element | Andrei Mihnea, Deepak C. Sekar, George Samachisa, Li Xiao | 2013-11-05 |
| 8565015 | Methods of programming two terminal memory cells | Tyler Thorp | 2013-10-22 |
| 8553476 | Three dimensional memory system with page of data across word lines | Tianhong Yan, Luca Fasoli | 2013-10-08 |
| 8547720 | Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines | George Samachisa, Luca Fasoli, Masaaki Higashitani | 2013-10-01 |
| 8547725 | Method of programming a nonvolatile memory cell by reverse biasing a diode steering element to set a storage element | Tanmay Kumar, Pankaj Kalra, Jingyan Zhang | 2013-10-01 |
| 8536015 | Memory cell that includes a carbon-based memory element and methods of forming the same | Alper Ilkbahar, April D. Schricker | 2013-09-17 |
| 8531904 | Methods and apparatus for extending the effective thermal operating range of a memory | Tyler Thorp | 2013-09-10 |
| 8509025 | Memory array circuit incorporating multiple array block selection and related method | Luca Fasoli | 2013-08-13 |
| 8498146 | Programming reversible resistance switching elements | Deepak C. Sekar, Klaus Schuegraf | 2013-07-30 |
| 8482960 | Multi-bit resistance-switching memory cell | — | 2013-07-09 |
| 8466068 | Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography | — | 2013-06-18 |
| 8462580 | Memory system with reversible resistivity-switching using pulses of alternatrie polarity | Peter Rabkin, George Samachisa | 2013-06-11 |
| 8441849 | Reducing programming time of a memory cell | Tyler Thorp | 2013-05-14 |
| 8385141 | Structure and method for biasing phase change memory array for reliable writing | — | 2013-02-26 |
| 8379437 | Flexible multi-pulse set operation for phase-change memories | Tyler Thorp | 2013-02-19 |
| 8355271 | Memory system with reversible resistivity-switching using pulses of alternate polarity | Peter Rabkin, George Samachisa | 2013-01-15 |
| 8350299 | Memory with high dielectric constant antifuses adapted for use at low voltage | Xiaoyu Yang, Feng Li, Albert T. Meeks | 2013-01-08 |
| 8320196 | Semiconductor memory with improved block switching | Thomas Kang-Po Yan, Luca Fasoli | 2012-11-27 |
| 8314023 | Methods involving memory with high dielectric constant antifuses adapted for use at low voltage | Xiaoyu Yang, Feng Li, Albert T. Meeks | 2012-11-20 |
| 8309415 | Methods and apparatus for increasing memory density using diode layer sharing | Huiwen Xu, Er-Xuan Ping | 2012-11-13 |