Issued Patents All Time
Showing 26–50 of 271 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8908444 | Erase for 3D non-volatile memory with sequential selection of word lines | Xiying Costa, Seung Yu, Haibo Li, Man Lung Mui | 2014-12-09 |
| 8885381 | Three dimensional non-volatile storage with dual gated vertical select devices | — | 2014-11-11 |
| 8885389 | Continuous mesh three dimensional non-volatile storage with vertical select devices | — | 2014-11-11 |
| 8883569 | Continuous mesh three dimensional non-volatile storage with vertical select devices | — | 2014-11-11 |
| 8861280 | Erase for 3D non-volatile memory with sequential selection of word lines | Xiying Costa, Seung Yu, Haibo Li, Man Lung Mui | 2014-10-14 |
| 8861258 | Set/reset algorithm which detects and repairs weak cells in resistive-switching memory device | Zhida Lan, Thomas Kang-Po Yan | 2014-10-14 |
| 8848415 | Three dimensional non-volatile storage with multi block row selection | Tianhong Yan | 2014-09-30 |
| 8847200 | Memory cell comprising a carbon nanotube fabric element and a steering element | Scott Brad Herner | 2014-09-30 |
| 8848430 | Step soft program for reversible resistivity-switching elements | Xiying Costa, Abhijit Bandyopadhyay, Brian Le, Li Xiao, Tao Du +1 more | 2014-09-30 |
| 8841648 | Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same | Yung-Tin Chen, Andrei Mihnea, Luca Fasoli | 2014-09-23 |
| 8809128 | Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning | Christopher J. Petti, Yoichiro Tanaka | 2014-08-19 |
| 8773898 | Methods and apparatus for reducing programming time of a memory cell | Tyler Thorp | 2014-07-08 |
| 8766332 | Optimization of critical dimensions and pitch of patterned features in and above a substrate | James M. Cleeves | 2014-07-01 |
| 8755223 | Three dimensional non-volatile storage with asymmetrical vertical select devices | — | 2014-06-17 |
| 8750066 | Temperature compensation of conductive bridge memory arrays | George Samachisa | 2014-06-10 |
| 8741696 | Methods of forming pillars for memory cells using sequential sidewall patterning | Christopher J. Petti, Yoichiro Tanaka | 2014-06-03 |
| 8699293 | Non-volatile storage system with dual block programming | Tianhong Yan, Tz-Yi Liu | 2014-04-15 |
| 8693233 | Re-writable resistance-switching memory with balanced series stack | Henry Chien, Zhida Lan, Yung-Tin Chen | 2014-04-08 |
| 8686476 | Resistance-switching memory cells adapted for use at low voltage | Xiaoyu Yang, Feng Li, Albert T. Meeks | 2014-04-01 |
| 8679967 | Apparatus and methods of forming memory lines and structures using double sidewall patterning for four times half pitch relief patterning | Yoichiro Tanaka | 2014-03-25 |
| 8659932 | Single device driver circuit to control three-dimensional memory element array | — | 2014-02-25 |
| 8659028 | Three-dimensional memory device incorporating segmented array line memory array | Alper Ilkbahar, Luca Fasoli | 2014-02-25 |
| 8649206 | Multi-bit resistance-switching memory cell | — | 2014-02-11 |
| 8637870 | Three-dimensional memory device incorporating segmented array line memory array | Alper Ilkbahar, Luca Fasoli | 2014-01-28 |
| 8633528 | Methods and apparatus for increasing memory density using diode layer sharing | Huiwen Xu, Er-Xuan Ping | 2014-01-21 |