Issued Patents All Time
Showing 1–25 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411606 | High capacity memory circuit with low effective latency | Youn Cheul Kim, Richard S. Chernicoff, Khandker N. Quader, Robert Norman, Sayeef Salahuddin +1 more | 2025-09-09 |
| 12324159 | Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays | Scott Brad Herner, Jie Zhou, Wu-Yi Henry Chien, Eli Harari | 2025-06-03 |
| 12245430 | Three-dimensional vertical nor flash thin-film transistor strings | Eli Harari | 2025-03-04 |
| 12073082 | High capacity memory circuit with low effective latency | Youn Cheul Kim, Richard S. Chernicoff, Khandker N. Quader, Robert Norman, Sayeef Salahuddin +1 more | 2024-08-27 |
| 11910612 | Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array | Scott Brad Herner, Jie Zhou, Wu-Yi Henry Chien, Eli Harari | 2024-02-20 |
| 11758727 | Three-dimensional vertical nor flash thin-film transistor strings | Eli Harari | 2023-09-12 |
| 11675500 | High capacity memory circuit with low effective latency | Youn Cheul Kim, Richard S. Chernicoff, Khandker N. Quader, Robert Norman, Sayeef Salahuddin +1 more | 2023-06-13 |
| 11610914 | Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays | Scott Brad Herner, Jie Zhou, Wu-Yi Henry Chien, Eli Harari | 2023-03-21 |
| 11398492 | Vertical thing-film transistor and application as bit-line connector for 3-dimensional memory arrays | Scott Brad Herner, Jie Zhou, Wu-Yi Henry Chien, Eli Harari | 2022-07-26 |
| 11049879 | Three-dimensional vertical NOR flash thin-film transistor strings | Eli Harari | 2021-06-29 |
| 10854634 | Three-dimensional vertical NOR flash thin-film transistor strings | Eli Harari | 2020-12-01 |
| 10796751 | State change detection for two-terminal memory | Sang Thanh Nguyen, Hagop Nazarian | 2020-10-06 |
| 10475511 | Read operation with data latch and signal termination for 1TNR memory array | Lin-Shih Liu, Sung Hyun Jo, Sang Thanh Nguyen, Hagop Nazarian | 2019-11-12 |
| 10283183 | Optimal write method for a ferroelectric memory | — | 2019-05-07 |
| 10199093 | State change detection for two-terminal memory utilizing current mirroring circuitry | Sang Thanh Nguyen, Hagop Nazarian | 2019-02-05 |
| 10134469 | Read operation with data latch and signal termination for 1TNR memory array | Lin-Shih Liu, Sung Hyun Jo, Sang Thanh Nguyen, Hagop Nazarian | 2018-11-20 |
| 10074427 | Shaped data associated with an erase operation | Idan Alrod, Noam Presman, Ariel Navon, Tz-Yi Liu | 2018-09-11 |
| 9972374 | Ferroelectric random access memory (FeRAM) array with segmented plate lines that are electrically-isolated from each other | — | 2018-05-15 |
| 9922709 | Memory hole bit line structures | Perumal Ratnam, Christopher J. Petti | 2018-03-20 |
| 9899085 | Non-volatile FeSRAM cell capable of non-destructive read operations | — | 2018-02-20 |
| 9837152 | Independent sense amplifier addressing and quota sharing in non-volatile memory | Gopinath Balakrishnan, Yibo Yin | 2017-12-05 |
| 9812204 | Ferroelectric memory cell without a plate line | Yung-Tin Chen | 2017-11-07 |
| 9734903 | Disturb condition detection for a resistive random access memory | Ran Zamir, Eran Sharon, Idan Alrod, Ariel Navon, Tz-Yi Liu | 2017-08-15 |
| 9721653 | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture | George Samachisa | 2017-08-01 |
| 9715925 | Methods and apparatus for vertical cross point re-RAM array bias calibration | Chang Hua Siau | 2017-07-25 |