Issued Patents All Time
Showing 1–25 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12402319 | Three-dimensional memory string array of thin-film ferroelectric transistors formed with an oxide semiconductor channel | Eli Harari | 2025-08-26 |
| 12324159 | Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays | Tianhong Yan, Scott Brad Herner, Jie Zhou, Eli Harari | 2025-06-03 |
| 12295143 | Methods for forming multilayer horizontal NOR-type thin-film memory strings | Scott Brad Herner, Jie Zhou, Eli Harari | 2025-05-06 |
| 12256547 | Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensional NOR memory string array | Scott Brad Herner, Christopher J. Petti, George Samachisa | 2025-03-18 |
| 12183834 | Cool electron erasing in thin-film storage transistors | Sayeef Salahuddin, George Samachisa, Eli Harari | 2024-12-31 |
| 12160996 | Three-dimensional memory string array of thin-film ferroelectric transistors | Christopher J. Petti, Vinod R. Purayath, George Samachisa, Eli Harari | 2024-12-03 |
| 12150304 | Methods for forming multi-layer vertical NOR-type memory string arrays | Scott Brad Herner, Jie Zhou, Eli Harari | 2024-11-19 |
| 12096630 | Staircase structures for electrically connecting multiple horizontal conductive layers of a 3-dimensional memory device | Raul-Adrian Cernea, Eli Harari | 2024-09-17 |
| 12052867 | 3-dimensional NOR memory array with very fine pitch: device and method | Eli Harari, Scott Brad Herner | 2024-07-30 |
| 11917821 | Process for a 3-dimensional array of horizontal nor-type memory strings | Vinod R. Purayath | 2024-02-27 |
| 11910612 | Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array | Tianhong Yan, Scott Brad Herner, Jie Zhou, Eli Harari | 2024-02-20 |
| 11844204 | Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array | Vinod R. Purayath, Jie Zhou, Eli Harari | 2023-12-12 |
| 11844217 | Methods for forming multi-layer vertical nor-type memory string arrays | Scott Brad Herner, Jie Zhou, Eli Harari | 2023-12-12 |
| 11839086 | 3-dimensional memory string array of thin-film ferroelectric transistors | Christopher J. Petti, Vinod R. Purayath, George Samachisa, Eli Harari | 2023-12-05 |
| 11751392 | Fabrication method for a 3-dimensional NOR memory array | Eli Harari, Scott Brad Herner | 2023-09-05 |
| 11730000 | 3-dimensional nor string arrays in segmented stacks | Eli Harari | 2023-08-15 |
| 11729980 | 3-dimensional NOR memory array architecture and methods for fabrication thereof | Eli Harari, Scott Brad Herner | 2023-08-15 |
| 11705496 | Charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of a memory cell in a 3-dimensional NOR memory string array | Scott Brad Herner, Eli Harari | 2023-07-18 |
| 11610914 | Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays | Tianhong Yan, Scott Brad Herner, Jie Zhou, Eli Harari | 2023-03-21 |
| 11610909 | Processes for forming 3-dimensional horizontal NOR memory arrays | Eli Harari | 2023-03-21 |
| 11557606 | Epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof | Chenming Hu, Eli Harari | 2023-01-17 |
| 11515309 | Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array | Vinod R. Purayath, Jie Zhou, Eli Harari | 2022-11-29 |
| 11515432 | Cool electron erasing in thin-film storage transistors | Sayeef Salahuddin, George Samachisa, Eli Harari | 2022-11-29 |
| 11404431 | Methods for forming multilayer horizontal NOR-type thin-film memory strings | Scott Brad Herner, Jie Zhou, Eli Harari | 2022-08-02 |
| 11398492 | Vertical thing-film transistor and application as bit-line connector for 3-dimensional memory arrays | Tianhong Yan, Scott Brad Herner, Jie Zhou, Eli Harari | 2022-07-26 |