Issued Patents All Time
Showing 1–25 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12315565 | Three-dimensional memory structure fabricated using repeated active stack sections | Shohei Kamisaka, Jie Zhou | 2025-05-27 |
| 12205645 | Three-dimensional memory structure fabrication using channel replacement | Shohei Kamisaka | 2025-01-21 |
| 12160996 | Three-dimensional memory string array of thin-film ferroelectric transistors | Christopher J. Petti, George Samachisa, Wu-Yi Henry Chien, Eli Harari | 2024-12-03 |
| 11917821 | Process for a 3-dimensional array of horizontal nor-type memory strings | Wu-Yi Henry Chien | 2024-02-27 |
| 11844204 | Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array | Jie Zhou, Wu-Yi Henry Chien, Eli Harari | 2023-12-12 |
| 11839086 | 3-dimensional memory string array of thin-film ferroelectric transistors | Christopher J. Petti, George Samachisa, Wu-Yi Henry Chien, Eli Harari | 2023-12-05 |
| 11751391 | Methods for fabricating a 3-dimensional memory structure of nor memory strings | Yosuke Nosho, Shohei Kamisaka, Michiru Nakane, Eli Harari | 2023-09-05 |
| 11515309 | Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array | Jie Zhou, Wu-Yi Henry Chien, Eli Harari | 2022-11-29 |
| 11217600 | Process for a 3-dimensional array of horizontal NOR-type memory strings | Wu-Yi Henry Chien | 2022-01-04 |
| 10790298 | Methods and apparatus for three-dimensional NAND structure fabrication | — | 2020-09-29 |
| 10541246 | 3D flash memory cells which discourage cross-cell electrical tunneling | — | 2020-01-21 |
| 10529737 | Accommodating imperfectly aligned memory holes | — | 2020-01-07 |
| 10468259 | Charge-trap layer separation and word-line isolation in a 3-D NAND structure | Nitin K. Ingle | 2019-11-05 |
| 10325923 | Accommodating imperfectly aligned memory holes | — | 2019-06-18 |
| 10319739 | Accommodating imperfectly aligned memory holes | — | 2019-06-11 |
| 9960045 | Charge-trap layer separation and word-line isolation for enhanced 3-D NAND structure | Nitin K. Ingle | 2018-05-01 |
| 9773695 | Integrated bit-line airgap formation and gate stack post clean | Randhir P. S. Thakur, Shankar Venkataraman, Nitin K. Ingle | 2017-09-26 |
| 9698149 | Non-volatile memory with flat cell structures and air gap isolation | George Matamis, Henry Chien, James Kai, Yuan Zhang | 2017-07-04 |
| 9552991 | Trench vertical NAND and method of making thereof | Akira Matsudaira, James Kai, Yuan Zhang, Donovan Lee | 2017-01-24 |
| 9548311 | Non-volatile storage element with suspended charge storage region | Donovan Lee, James Kai | 2017-01-17 |
| 9496167 | Integrated bit-line airgap formation and gate stack post clean | Randhir P. S. Thakur, Shankar Venkataraman, Nitin K. Ingle | 2016-11-15 |
| 9466644 | Resistance-switching memory cell with multiple raised structures in a bottom electrode | George Matamis, James Kai, Yuan Zhang, Henry Chien | 2016-10-11 |
| 9460958 | Air gap isolation in non-volatile memory | Hiroyuki Kinoshita, Tuan Pham | 2016-10-04 |
| 9449846 | Vertical gate separation | Jie Liu, Xikun Wang, Anchuan Wang, Nitin K. Ingle | 2016-09-20 |
| 9437813 | Method for forming resistance-switching memory cell with multiple electrodes using nano-particle hard mask | George Matamis, James Kai, Yuan Zhang, Henry Chien | 2016-09-06 |