Issued Patents All Time
Showing 26–50 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9659642 | State change detection for two-terminal memory during application of a state-changing stimulus | Sang Thanh Nguyen, Cung Vu, Dzung H. Nguyen, Hagop Nazarian, John T. Nguyen | 2017-05-23 |
| 9595325 | Apparatus and methods for sensing hard bit and soft bits | Chang Hua Siau, Jeffrey Koon Yee Lee, Yingchang Chen, Gopinath Balakrishnan, Tz-Yi Liu | 2017-03-14 |
| 9583183 | Reading resistive random access memory based on leakage current | Omer Fainzilber, Eran Sharon, Idan Alrod, Ariel Navon, Tz-Yi Liu | 2017-02-28 |
| 9564215 | Independent sense amplifier addressing and quota sharing in non-volatile memory | Gopinath Balakrishnan, Yibo Yin | 2017-02-07 |
| 9543009 | Multiple layer forming scheme for vertical cross point reram | Chang Hua Siau | 2017-01-10 |
| 9484093 | Controlling adjustable resistance bit lines connected to word line combs | Perumal Ratnam, Christopher J. Petti | 2016-11-01 |
| 9484089 | Dual polarity read operation | Alexander Bazarsky, Stella Achtenberg, Eran Sharon, Ariel Navon, Idan Alrod +1 more | 2016-11-01 |
| 9472280 | Vertical cross point reram forming method | Chang Hua Siau | 2016-10-18 |
| 9455301 | Setting channel voltages of adjustable resistance bit line structures using dummy word lines | Perumal Ratnam, Christopher J. Petti | 2016-09-27 |
| 9442663 | Independent set/reset programming scheme | Tz-Yi Liu | 2016-09-13 |
| 9373396 | Side wall bit line structures | Perumal Ratnam, Christopher J. Petti | 2016-06-21 |
| 9318194 | Apparatus and methods for sensing hard bit and soft bits | Chang Hua Siau, Jeffrey Koon Yee Lee, Yingchang Chen, Gopinath Balakrishnan, Tz-Yi Liu | 2016-04-19 |
| 9312002 | Methods for programming ReRAM devices | Ariel Navon, Idan Alrod, Eran Sharon, Ishai Ilani, Tz-Yi Liu +1 more | 2016-04-12 |
| 9240235 | Mitigating disturb effects for non-volatile memory | Idan Alrod, Eran Sharon, Tz-Yi Liu, Menahem Lasser | 2016-01-19 |
| 9236122 | Shared-gate vertical-TFT for vertical bit line array | George Samachisa, Tz-Yi Liu, Tim Chen, Perumal Ratnam | 2016-01-12 |
| 9202566 | Vertical cross point reram forming method | Chang Hua Siau | 2015-12-01 |
| 9196362 | Multiple layer forming scheme for vertical cross point reram | Chang Hua Siau | 2015-11-24 |
| 9165649 | Systems and methods of shaping data | Eran Sharon, Tz-Yi Liu, Idan Alrod | 2015-10-20 |
| 9123392 | Non-volatile 3D memory with cell-selectable word line decoding | Roy E. Scheuerlein | 2015-09-01 |
| 9053766 | Three dimensional memory system with intelligent select circuit | — | 2015-06-09 |
| 8982597 | Memory system with sectional data lines | Luca Fasoli | 2015-03-17 |
| 8913413 | Memory system with sectional data lines | Luca Fasoli | 2014-12-16 |
| 8848415 | Three dimensional non-volatile storage with multi block row selection | Roy E. Scheuerlein | 2014-09-30 |
| 8824191 | Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof | George Samachisa, Luca Fasoli, Yan Li | 2014-09-02 |
| 8780651 | Continuous programming of non-volatile memory | Luca Fasoli | 2014-07-15 |