Issued Patents All Time
Showing 1–25 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| RE46348 | Program cycle skip | Gopinath Balakrishnan, Tz-Yi Liu, Yuheng Zhang, Yan Li | 2017-03-21 |
| RE46154 | Page buffer program command and methods to reprogram pages without re-inputting data to a memory device | Yuheng Zhang, Gopinath Balakrishnan | 2016-09-20 |
| 9245629 | Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines | George Samachisa, Masaaki Higashitani, Roy E. Scheuerlein | 2016-01-26 |
| 9105576 | Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same | Yung-Tin Chen, Andrei Mihnea, Roy E. Scheuerlein | 2015-08-11 |
| 8982597 | Memory system with sectional data lines | Tianhong Yan | 2015-03-17 |
| 8913413 | Memory system with sectional data lines | Tianhong Yan | 2014-12-16 |
| 8841648 | Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same | Yung-Tin Chen, Andrei Mihnea, Roy E. Scheuerlein | 2014-09-23 |
| 8824191 | Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof | George Samachisa, Yan Li, Tianhong Yan | 2014-09-02 |
| 8780651 | Continuous programming of non-volatile memory | Tianhong Yan | 2014-07-15 |
| 8711596 | Memory system with data line switching scheme | Tianhong Yan | 2014-04-29 |
| 8659028 | Three-dimensional memory device incorporating segmented array line memory array | Roy E. Scheuerlein, Alper Ilkbahar | 2014-02-25 |
| 8638586 | Memory system with data line switching scheme | Tianhong Yan | 2014-01-28 |
| 8637870 | Three-dimensional memory device incorporating segmented array line memory array | Roy E. Scheuerlein, Alper Ilkbahar | 2014-01-28 |
| 8553476 | Three dimensional memory system with page of data across word lines | Tianhong Yan, Roy E. Scheuerlein | 2013-10-08 |
| 8547720 | Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines | George Samachisa, Masaaki Higashitani, Roy E. Scheuerlein | 2013-10-01 |
| 8526237 | Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof | George Samachisa, Yan Li, Tianhong Yan | 2013-09-03 |
| 8509025 | Memory array circuit incorporating multiple array block selection and related method | Roy E. Scheuerlein | 2013-08-13 |
| 8427890 | Program cycle skip | Gopinath Balakrishnan, Tz-Yi Liu, Yuheng Zhang, Yan Li | 2013-04-23 |
| 8395948 | Program cycle skip | Gopinath Balakrishnan, Tz-Yi Liu, Yuheng Zhang, Yan Li | 2013-03-12 |
| 8397024 | Page buffer program command and methods to reprogram pages without re-inputting data to a memory device | Yuheng Zhang, Gopinath Balakrishnan | 2013-03-12 |
| 8358528 | Memory system with sectional data lines | Tianhong Yan | 2013-01-22 |
| 8320196 | Semiconductor memory with improved block switching | Thomas Kang-Po Yan, Roy E. Scheuerlein | 2012-11-27 |
| 8310892 | Capacitive discharge method for writing to non-volatile memory | Roy E. Scheuerlein, Tianhong Yan | 2012-11-13 |
| 8279650 | Memory system with data line switching scheme | Tianhong Yan | 2012-10-02 |
| 8279704 | Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same | Roy E. Scheuerlein | 2012-10-02 |