Issued Patents All Time
Showing 51–75 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7570523 | Method for using two data busses for memory array block selection | Roy E. Scheuerlein, Christopher J. Petti | 2009-08-04 |
| 7558140 | Method for using a spatially distributed amplifier circuit | Ali Al-Shamma, Kenneth So | 2009-07-07 |
| 7554406 | Spatially distributed amplifier circuit | Ali Al-Shamma, Kenneth So | 2009-06-30 |
| 7554832 | Passive element memory array incorporating reversible polarity word line and bit line decoders | Christopher J. Petti, Roy E. Scheuerlein | 2009-06-30 |
| 7542338 | Method for reading a multi-level passive element memory cell array | Roy E. Scheuerlein, Tyler Thorp | 2009-06-02 |
| 7542370 | Reversible polarity decoder circuit | Tianhong Yan, Roy E. Scheuerlein | 2009-06-02 |
| 7542337 | Apparatus for reading a multi-level passive element memory cell array | Roy E. Scheuerlein, Tyler Thorp | 2009-06-02 |
| 7525869 | Method for using a reversible polarity decoder circuit | Tianhong Yan, Roy E. Scheuerlein | 2009-04-28 |
| 7508714 | Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block | Roy E. Scheuerlein, En-Hsing Chen, Sucheta Nallamothu, Maitreyee Mahajani, Andrew J. Walker | 2009-03-24 |
| 7505321 | Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same | Roy E. Scheuerlein, Christopher J. Petti, Andrew J. Walker, En-Hsing Chen, Sucheta Nallamothu +2 more | 2009-03-17 |
| 7499366 | Method for using dual data-dependent busses for coupling read/write circuits to a memory array | Roy E. Scheuerlein | 2009-03-03 |
| 7486587 | Dual data-dependent busses for coupling read/write circuits to a memory array | Roy E. Scheuerlein | 2009-02-03 |
| 7463546 | Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders | Christopher J. Petti, Roy E. Scheuerlein | 2008-12-09 |
| 7463536 | Memory array incorporating two data busses for memory array block selection | Roy E. Scheuerlein, Christopher J. Petti | 2008-12-09 |
| 7433233 | NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same | En-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar | 2008-10-07 |
| 7420850 | Method for controlling current during programming of memory cells | — | 2008-09-02 |
| 7420851 | Memory device for controlling current during programming of memory cells | — | 2008-09-02 |
| 7391638 | Memory device for protecting memory cells during programming | Tyler Thorp | 2008-06-24 |
| 7383476 | System architecture and method for three-dimensional memory | Matthew P. Crowley, Alper Ilkbahar, Mark G. Johnson, Bendik Kleveland, Thomas H. Lee +1 more | 2008-06-03 |
| 7359279 | Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers | Roy E. Scheuerlein | 2008-04-15 |
| 7298665 | Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation | Kenneth So, Roy E. Scheuerlein | 2007-11-20 |
| 7286439 | Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders | Kenneth So | 2007-10-23 |
| 7272052 | Decoding circuit for non-binary groups of memory line drivers | Roy E. Scheuerlein, Christopher J. Petti | 2007-09-18 |
| 7233522 | NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same | En-Hsing Chen, Andrew J. Walker, Roy E. Scheuerlein, Sucheta Nallamothu, Alper Ilkbahar | 2007-06-19 |
| 7233024 | Three-dimensional memory device incorporating segmented bit line memory array | Roy E. Scheuerlein, Alper Ilkbahar | 2007-06-19 |