Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9361196 | Memory device with background built-in self-repair using background built-in self-testing | Dipak K. Sikdar, Rajesh Chopra, Jay B. Patel | 2016-06-07 |
| 9037928 | Memory device with background built-in self-testing and background built-in self-repair | Dipak K. Sikdar, Rajesh Chopra, Jay B. Patel | 2015-05-19 |
| 8219778 | Virtual memory interface | Michael J. Palladino, Carl Gyllenhammer | 2012-07-10 |
| 7978448 | Hybrid circuit for circuit protection and switching | Yuen Hui Chee, Thomas H. Lee | 2011-07-12 |
| 7759916 | Regulator with device performance dynamic mode selection | — | 2010-07-20 |
| 7728679 | Calibration of voltage controlled oscillators | Stanley Bo-Ting Wang, Thomas H. Lee | 2010-06-01 |
| 7603244 | Calibration of voltage controlled oscillators | Stanley Bo-Ting Wang, Thomas H. Lee | 2009-10-13 |
| 7570035 | Voltage regulator with a hybrid control loop | — | 2009-08-04 |
| 7564707 | One-time programmable non-volatile memory | — | 2009-07-21 |
| 7482888 | Fast startup resonant element oscillator | — | 2009-01-27 |
| 7415369 | Calibration of voltage-controlled oscillators | Stanley Bo-Ting Wang, Thomas H. Lee | 2008-08-19 |
| 7383476 | System architecture and method for three-dimensional memory | Matthew P. Crowley, Luca Fasoli, Alper Ilkbahar, Mark G. Johnson, Thomas H. Lee +1 more | 2008-06-03 |
| 7219271 | Memory device and method for redundancy/self-repair | Alper Ilkbahar, Roy E. Scheuerlein | 2007-05-15 |
| 7212454 | Method and apparatus for programming a memory array | Tae Hee Lee, Seung Yu, Chia Yang, Feng Li, Xiaoyu Yang | 2007-05-01 |
| 7180949 | High-speed chip-to-chip communication interface | Eric T. Anderson, Gunes Aybay, Philip Ferolito | 2007-02-20 |
| 7134056 | High-speed chip-to-chip communication interface with signal trace routing and phase offset detection | Eric T. Anderson, Gunes Aybay, Philip Ferolito | 2006-11-07 |
| 7057958 | Method and system for temperature compensation for memory cells with temperature-dependent behavior | Kenneth So, Luca Fasoli | 2006-06-06 |
| 6954394 | Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions | N. Johan Knall, Roy E. Scheuerlein, James M. Cleeves, Mark G. Johnson | 2005-10-11 |
| 6894936 | Memory device and method for selectable sub-array activation | Roy E. Scheuerlein | 2005-05-17 |
| 6816410 | Method for programming a three-dimensional memory array incorporating serial chain diode stack | Roy E. Scheuerlein | 2004-11-09 |
| 6784517 | Three-dimensional memory array incorporating serial chain diode stack | N. Knall | 2004-08-31 |
| 6781878 | Dynamic sub-array group selection scheme | Roy E. Scheuerlein | 2004-08-24 |
| 6767816 | Method for making a three-dimensional memory array incorporating serial chain diode stack | N. Johan Knall | 2004-07-27 |
| 6754102 | Method for programming a three-dimensional memory array incorporating serial chain diode stack | Roy E. Scheuerlein | 2004-06-22 |
| 6724665 | Memory device and method for selectable sub-array activation | Roy E. Scheuerlein | 2004-04-20 |