Issued Patents All Time
Showing 26–50 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8238174 | Continuous programming of non-volatile memory | Tianhong Yan | 2012-08-07 |
| 8233309 | Non-volatile memory array architecture incorporating 1T-1R near 4F2 memory cell | — | 2012-07-31 |
| 8223525 | Page register outside array and sense amplifier interface | Gopinath Balakrishnan, Jeffrey Koon Yee Lee, Yuheng Zhang, Tz-Yi Liu | 2012-07-17 |
| 8213243 | Program cycle skip | Gopinath Balakrishnan, Tz-Yi Liu, Yuheng Zhang, Yan Li | 2012-07-03 |
| 8199576 | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture | George Samachisa | 2012-06-12 |
| 8149607 | Rewritable memory device with multi-level, write-once memory cells | Roy E. Scheuerlein | 2012-04-03 |
| 8130528 | Memory system with sectional data lines | Tianhong Yan | 2012-03-06 |
| 8111539 | Smart detection circuit for writing to non-volatile storage | Tianhong Yan, Jeffrey Koon Yee Lee | 2012-02-07 |
| 8059447 | Capacitive discharge method for writing to non-volatile memory | Roy E. Scheuerlein, Tianhong Yan | 2011-11-15 |
| 8050109 | Semiconductor memory with improved memory block switching | Thomas Kang-Po Yan, Roy E. Scheuerlein | 2011-11-01 |
| 8027209 | Continuous programming of non-volatile memory | Tianhong Yan | 2011-09-27 |
| 8004927 | Reversible-polarity decoder circuit and method | Roy E. Scheuerlein | 2011-08-23 |
| 7996736 | Bad page marking strategy for fast readout in memory | Aldo Bottelli | 2011-08-09 |
| 7966532 | Method for selectively retrieving column redundancy data in memory device | Aldo Bottelli, Doug Sojourner | 2011-06-21 |
| 7940554 | Reduced complexity array line drivers for 3D matrix arrays | Roy E. Scheuerlein | 2011-05-10 |
| 7885091 | Limited charge delivery for programming non-volatile storage elements | Andrei Mihnea | 2011-02-08 |
| 7733685 | Cross point memory cell with distributed diodes and method of making same | Roy E. Scheuerlein | 2010-06-08 |
| 7696804 | Method for incorporating transistor snap-back protection in a level shifter circuit | Tyler Thorp | 2010-04-13 |
| 7696805 | Level shifter circuit incorporating transistor snap-back protection | Tyler Thorp | 2010-04-13 |
| 7697366 | Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers | Roy E. Scheuerlein | 2010-04-13 |
| 7633829 | Hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders | Kenneth So | 2009-12-15 |
| 7633828 | Hierarchical bit line bias bus for block selectable memory array | Roy E. Scheuerlein | 2009-12-15 |
| 7596050 | Method for using a hierarchical bit line bias bus for block selectable memory array | Roy E. Scheuerlein | 2009-09-29 |
| 7593249 | Memory device for protecting memory cells during programming | Tyler Thorp | 2009-09-22 |
| 7589989 | Method for protecting memory cells during programming | Tyler Thorp | 2009-09-15 |