Issued Patents All Time
Showing 25 most recent of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11528222 | Decentralized control plane | Maheedhar Nallapareddy, Akshay Katrekar, Aarti Lolage, Nikhil Ravindra Rajguru, Shyam Ramachandran | 2022-12-13 |
| 10931572 | Decentralized control plane | Maheedhar Nallapareddy, Akshay Katrekar, Aarti Lolage, Nikhil Ravindra Rajguru, Shyam Ramachandran | 2021-02-23 |
| 10489700 | Neuromorphic logic for an array of high on/off ratio non-volatile memory cells | Mehdi Asnaashari, Hagop Nazarian, Sung Hyun Jo | 2019-11-26 |
| 10388870 | Barrier modulated cell structures with intrinsic vertical bit line architecture | Perumal Ratnam, Christopher J. Petti | 2019-08-20 |
| 10340449 | Resistive memory device containing carbon barrier and method of making thereof | Ming-Che Wu, Alvaro Padilla | 2019-07-02 |
| 10283708 | Methods and apparatus for three-dimensional nonvolatile memory | Ming-Che Wu, Deepak Kamalanathan, Juan Saenz | 2019-05-07 |
| 10283567 | Methods and apparatus for three-dimensional nonvolatile memory | Juan Saenz, Deepak Kamalanathan, Guangle Zhou, Ming-Che Wu | 2019-05-07 |
| 10276792 | Low power barrier modulated cell for storage class memory | Ming-Che Wu | 2019-04-30 |
| 10115819 | Recessed high voltage metal oxide semiconductor transistor for RRAM cell | Harry Yue Gee, Natividad Vasquez, Steven Patrick Maxwell, Sundar Narayanan | 2018-10-30 |
| 10109680 | Methods and apparatus for three-dimensional nonvolatile memory | Sebastian J. M. Wicklein, Juan Saenz, Srikanth Ranganathan, Ming-Che Wu | 2018-10-23 |
| 10032908 | Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereof | Perumal Ratnam, Christopher J. Petti, Juan Saenz, Guangle Zhou, Abhijit Bandyopadhyay | 2018-07-24 |
| 9953697 | Volatile memory device employing a resistive memory element | Alper Ilkbahar | 2018-04-24 |
| 9923140 | Low power barrier modulated cell for storage class memory | Ming-Che Wu | 2018-03-20 |
| 9806256 | Resistive memory device having sidewall spacer electrode and method of making thereof | Ming-Che Wu, Chuanbin Pan, Guangle Zhou | 2017-10-31 |
| 9805794 | Enhanced erasing of two-terminal memory | Zhi Li, Sung Hyun Jo | 2017-10-31 |
| 9793474 | Low temperature P+ polycrystalline silicon material for non-volatile memory device | Xin Sun, Sung Hyun Jo | 2017-10-17 |
| 9768180 | Methods and apparatus for three-dimensional nonvolatile memory | Guangle Zhou, Yubao Li, Yangyin Chen | 2017-09-19 |
| 9735358 | Noble metal / non-noble metal electrode for RRAM applications | Sung Hyun Jo, Kuk-Hwan Kim | 2017-08-15 |
| 9729155 | Field programmable gate array utilizing two-terminal non-volatile memory | Hagop Nazarian, Sang Thanh Nguyen | 2017-08-08 |
| 9673255 | Resistive memory device and fabrication methods | Sung Hyun Jo, Kuk-Hwan Kim | 2017-06-06 |
| 9613694 | Enhanced programming of two-terminal memory | Zhi Li, Sung Hyun Jo | 2017-04-04 |
| 9502102 | MLC OTP operation with diode behavior in ZnO RRAM devices for 3D memory | Sung Hyun Jo | 2016-11-22 |
| 9472301 | Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same | Abhijit Bandyopadhyay, Scott Brad Herner, Christopher J. Petti, Roy E. Scheuerlein | 2016-10-18 |
| 9373410 | MLC OTP operation in A-Si RRAM | — | 2016-06-21 |
| 9343668 | Low temperature in-situ doped silicon-based conductor material for memory cell | Steve Maxwell, Sundar Narayanan, Sung Hyun Jo | 2016-05-17 |