Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10847579 | Method for fabricating an array of 4F2 resistive non-volatile memory in a NAND architecture | Hagop Nazarian | 2020-11-24 |
| 10453896 | 4F2 resistive non-volatile memory formed in a NAND architecture | Hagop Nazarian | 2019-10-22 |
| 10319908 | Integrative resistive memory in backend metal layers | Sundar Narayanan, Steve Maxwell, Natividad Vasquez | 2019-06-11 |
| 10290801 | Scalable silicon based resistive memory device | Sundar Narayanan, Steve Maxwell, Natividad Vasquez | 2019-05-14 |
| 10115819 | Recessed high voltage metal oxide semiconductor transistor for RRAM cell | Tanmay Kumar, Natividad Vasquez, Steven Patrick Maxwell, Sundar Narayanan | 2018-10-30 |
| 10109718 | Method for manufacturing a semiconductor device | Umesh Sharma, Der Min Liou, David D. Marreiro, Sudhama C. Shastri | 2018-10-23 |
| 10096653 | Monolithically integrated resistive memory using integrated-circuit foundry compatible processes | Sundar Narayanan, Steve Maxwell, Natividad Vasquez | 2018-10-09 |
| 10062845 | Flatness of memory cell surfaces | Zhen Gu, Natividad Vasquez, Sundar Narayanan | 2018-08-28 |
| 9741765 | Monolithically integrated resistive memory using integrated-circuit foundry compatible processes | Sundar Narayanan, Steve Maxwell, Natividad Vasquez | 2017-08-22 |
| 9698201 | High density selector-based non volatile memory cell and fabrication | Hagop Nazarian, Sung Hyun Jo | 2017-07-04 |
| 9685483 | Selector-based non-volatile cell fabrication utilizing IC-foundry compatible process | Hagop Nazarian, Sung Hyun Jo | 2017-06-20 |
| 9601690 | Sub-oxide interface layer for two-terminal memory | Mark Clark, Steven Patrick Maxwell, Sung Hyun Jo, Natividad Vasquez | 2017-03-21 |
| 9595670 | Resistive random access memory (RRAM) cell and method for forming the RRAM cell | Steven Patrick Maxwell, Natividad Vasquez, Sundar Narayanan | 2017-03-14 |
| 9583701 | Methods for fabricating resistive memory device switching material using ion implantation | Steven Patrick Maxwell, Natividad Vasquez, Mark Clark | 2017-02-28 |
| 9564424 | ESD device and structure therefor | David D. Marreiro, Yupeng Chen, Ralph N. Wall, Umesh Sharma | 2017-02-07 |
| 9437814 | Mitigating damage from a chemical mechanical planarization process | Majid Milani, Natividad Vasquez, Steven Patrick Maxwell, Sundar Narayanan | 2016-09-06 |
| 9425046 | Method for surface roughness reduction after silicon germanium thin film deposition | Steven Patrick Maxwell, Natividad Vasquez, Sundar Narayanan | 2016-08-23 |
| 9362499 | Three dimension programmable resistive random accessed memory array with shared bitline and method | Sung Hyun Jo, Hagop Nazarian, Scott Brad Herner | 2016-06-07 |
| 9337178 | Method of forming an ESD device and structure therefor | David D. Marreiro, Yupeng Chen, Ralph N. Wall, Umesh Sharma | 2016-05-10 |
| 9166163 | Sub-oxide interface layer for two-terminal memory | Mark Clark, Steven Patrick Maxwell, Sung Hyun Jo, Natividad Vasquez | 2015-10-20 |
| 8975609 | Three dimension programmable resistive random accessed memory array with shared bitline and method | Sung Hyun Jo, Hagop Nazarian, Scott Brad Herner | 2015-03-10 |
| 8946667 | Barrier structure for a silver based RRAM and method | Mark Clark, Steven Patrick Maxwell, Natividad Vasquez | 2015-02-03 |
| 8426306 | Three dimension programmable resistive random accessed memory array with shared bitline and method | Sung Hyun Jo, Hagop Nazarian, Scott Brad Herner | 2013-04-23 |
| 8199447 | Monolithic multi-channel ESD protection device | Wenjiang Zeng, Jeffrey C. Dunnihoo | 2012-06-12 |
| 7972521 | Method of making reliable wafer level chip scale package semiconductor devices | Umesh Sharma, Phillip Holland | 2011-07-05 |