GT

George S. Taylor

SG Silicon Graphics: 4 patents #100 of 758Top 15%
CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
GG Gemini Group: 1 patents #7 of 31Top 25%
MS Mips Computer Systems: 1 patents #12 of 25Top 50%
Overall (All Time): #408,283 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11797747 Identifying redundant logic based on clock gate enable condition Matthew Eaton, Zhuo Li, James Youren, Ji-Zheng Xu 2023-10-24
11354480 Determining clock gates for decloning based on simulation and satisfiability solver Matthew Eaton, Ji-Zheng Xu, Zhuo Li 2022-06-07
6857177 System for presetting shrink-fit tools 2005-02-22
6103307 Method and apparatus for mechanized application of a protective coating on siliceous surfaces Joel S. Miller 2000-08-15
5759618 Glass coating cmposition and method of application 1998-06-02
5738903 Glass coating composition and method of application Joel S. Miller 1998-04-14
5699551 Software invalidation in a multiple level, multiple cache system P. Michael Farmwald, Timothy P. Layman, Huy X. Ngo, Allen W. Roberts 1997-12-16
5555384 Rescheduling conflicting issued instructions by delaying one conflicting instruction into the same pipeline stage as a third non-conflicting instruction David B. Roberts, David Parry 1996-09-10
5542062 Cache memory system employing virtual address primary instruction and data caches and physical address secondary cache P. Michael Farmwald, Timothy P. Layman, Huy X. Ngo, Allen W. Roberts 1996-07-30
5333428 Method and apparatus for creating design insulated glass Barry K. Benedict 1994-08-02
5307477 Two-level cache memory system P. Michael Farmwald, Timothy P. Layman, Huy X. Ngo, Allen W. Roberts 1994-04-26
5226133 Two-level translation look-aside buffer using partial addresses for enhanced speed Michael Farmwald 1993-07-06