JY

James Youren

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
Overall (All Time): #2,615,829 of 4,157,543Top 65%
1
Patents All Time

Issued Patents All Time

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
11797747 Identifying redundant logic based on clock gate enable condition Matthew Eaton, George S. Taylor, Zhuo Li, Ji-Zheng Xu 2023-10-24