Issued Patents All Time
Showing 101–125 of 166 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7587585 | Flag management in processors enabled for speculative execution of micro-operation traces | Seungyoon Peter Song, Christopher Patrick Nelson | 2009-09-08 |
| 7568088 | Flag management in processors enabled for speculative execution of micro-operation traces | Seungyoon Peter Song, Christopher Patrick Nelson | 2009-07-28 |
| 7568089 | Flag management in processors enabled for speculative execution of micro-operation traces | Seungyoon Peter Song, Christopher Patrick Nelson | 2009-07-28 |
| 7533242 | Prefetch hardware efficiency via prefetch hint instructions | Laurent Moll, Jorel Hartman, Peter N. Glaskowsky, Seungyoon Peter Song | 2009-05-12 |
| 7512129 | Method and apparatus for implementing a switching unit including a bypass path | Edmund Chen, Ruchi Wadhawan | 2009-03-31 |
| 7493471 | Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready | Christopher Patrick Nelson | 2009-02-17 |
| 7490225 | Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number | Christopher Patrick Nelson | 2009-02-10 |
| 7490223 | Dynamic resource allocation among master processors that require service from a coprocessor | Christopher Patrick Nelson | 2009-02-10 |
| 7443759 | Reduced-power memory with per-sector ground control | Joseph B. Rowlands, Laurent Moll, Daniel Fung | 2008-10-28 |
| 7389408 | Microarchitecture for compact storage of embedded constants | Christopher Patrick Nelson | 2008-06-17 |
| 7389403 | Adaptive computing ensemble microprocessor architecture | Donald B. Alpert, Peter N. Glaskowsky, Seungyoon Peter Song | 2008-06-17 |
| 7349398 | Method and apparatus for out-of-order processing of packets | Edmund Chen, Stephan G. Meier | 2008-03-25 |
| 7349399 | Method and apparatus for out-of-order processing of packets using linked lists | Edmund Chen, Ruchi Wadhawan, Gregory G. Minshall | 2008-03-25 |
| 6970998 | Decoding suffix instruction specifying replacement destination for primary instruction | — | 2005-11-29 |
| 6732236 | Cache retry request queue | — | 2004-05-04 |
| 6499123 | Method and apparatus for debugging an integrated circuit | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, Dale R. Greenley +1 more | 2002-12-24 |
| 6453278 | Flexible implementation of a system management mode (SMM) in a processor | Frederick Daniel Weber | 2002-09-17 |
| 6425075 | Branch prediction device with two levels of branch prediction cache | David R. Stiles, Korbin S. Van Dyke | 2002-07-23 |
| 6336178 | RISC86 instruction set | — | 2002-01-01 |
| 6298438 | System and method for conditional moving an operand from a source register to destination register | John S. Thayer, Frederick Daniel Weber | 2001-10-02 |
| 6253306 | Prefetch instruction mechanism for processor | Amos Ben-Meir | 2001-06-26 |
| 6237083 | Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an instruction sequence | — | 2001-05-22 |
| 6212629 | Method and apparatus for executing string instructions | Harold L. McFarland, David R. Stiles, Korbin S. Van Dyke, Shrenik Mehta, Dale R. Greenley +1 more | 2001-04-03 |
| 6195744 | Unified multi-function operation scheduler for out-of-order execution in a superscaler processor | Amos Ben-Meir, Warren G. Stapleton | 2001-02-27 |
| 6173366 | Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage | John S. Thayer, Frederick Daniel Weber | 2001-01-09 |